mirror of https://gitee.com/openkylin/linux.git
272 lines
7.5 KiB
C
272 lines
7.5 KiB
C
/*
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* arch/arm/kernel/topology.c
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*
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* Copyright (C) 2011 Linaro Limited.
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* Written by: Vincent Guittot
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*
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* based on arch/sh/kernel/topology.c
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/arch_topology.h>
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/cpumask.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/percpu.h>
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#include <linux/node.h>
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#include <linux/nodemask.h>
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#include <linux/of.h>
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#include <linux/sched.h>
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#include <linux/sched/topology.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <asm/cpu.h>
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#include <asm/cputype.h>
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#include <asm/topology.h>
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/*
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* cpu capacity scale management
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*/
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/*
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* cpu capacity table
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* This per cpu data structure describes the relative capacity of each core.
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* On a heteregenous system, cores don't have the same computation capacity
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* and we reflect that difference in the cpu_capacity field so the scheduler
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* can take this difference into account during load balance. A per cpu
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* structure is preferred because each CPU updates its own cpu_capacity field
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* during the load balance except for idle cores. One idle core is selected
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* to run the rebalance_domains for all idle cores and the cpu_capacity can be
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* updated during this sequence.
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*/
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#ifdef CONFIG_OF
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struct cpu_efficiency {
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const char *compatible;
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unsigned long efficiency;
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};
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/*
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* Table of relative efficiency of each processors
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* The efficiency value must fit in 20bit and the final
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* cpu_scale value must be in the range
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* 0 < cpu_scale < 3*SCHED_CAPACITY_SCALE/2
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* in order to return at most 1 when DIV_ROUND_CLOSEST
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* is used to compute the capacity of a CPU.
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* Processors that are not defined in the table,
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* use the default SCHED_CAPACITY_SCALE value for cpu_scale.
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*/
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static const struct cpu_efficiency table_efficiency[] = {
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{"arm,cortex-a15", 3891},
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{"arm,cortex-a7", 2048},
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{NULL, },
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};
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static unsigned long *__cpu_capacity;
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#define cpu_capacity(cpu) __cpu_capacity[cpu]
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static unsigned long middle_capacity = 1;
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static bool cap_from_dt = true;
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/*
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* Iterate all CPUs' descriptor in DT and compute the efficiency
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* (as per table_efficiency). Also calculate a middle efficiency
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* as close as possible to (max{eff_i} - min{eff_i}) / 2
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* This is later used to scale the cpu_capacity field such that an
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* 'average' CPU is of middle capacity. Also see the comments near
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* table_efficiency[] and update_cpu_capacity().
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*/
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static void __init parse_dt_topology(void)
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{
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const struct cpu_efficiency *cpu_eff;
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struct device_node *cn = NULL;
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unsigned long min_capacity = ULONG_MAX;
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unsigned long max_capacity = 0;
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unsigned long capacity = 0;
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int cpu = 0;
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__cpu_capacity = kcalloc(nr_cpu_ids, sizeof(*__cpu_capacity),
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GFP_NOWAIT);
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for_each_possible_cpu(cpu) {
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const u32 *rate;
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int len;
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/* too early to use cpu->of_node */
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cn = of_get_cpu_node(cpu, NULL);
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if (!cn) {
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pr_err("missing device node for CPU %d\n", cpu);
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continue;
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}
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if (topology_parse_cpu_capacity(cn, cpu)) {
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of_node_put(cn);
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continue;
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}
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cap_from_dt = false;
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for (cpu_eff = table_efficiency; cpu_eff->compatible; cpu_eff++)
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if (of_device_is_compatible(cn, cpu_eff->compatible))
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break;
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if (cpu_eff->compatible == NULL)
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continue;
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rate = of_get_property(cn, "clock-frequency", &len);
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if (!rate || len != 4) {
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pr_err("%pOF missing clock-frequency property\n", cn);
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continue;
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}
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capacity = ((be32_to_cpup(rate)) >> 20) * cpu_eff->efficiency;
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/* Save min capacity of the system */
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if (capacity < min_capacity)
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min_capacity = capacity;
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/* Save max capacity of the system */
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if (capacity > max_capacity)
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max_capacity = capacity;
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cpu_capacity(cpu) = capacity;
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}
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/* If min and max capacities are equals, we bypass the update of the
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* cpu_scale because all CPUs have the same capacity. Otherwise, we
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* compute a middle_capacity factor that will ensure that the capacity
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* of an 'average' CPU of the system will be as close as possible to
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* SCHED_CAPACITY_SCALE, which is the default value, but with the
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* constraint explained near table_efficiency[].
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*/
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if (4*max_capacity < (3*(max_capacity + min_capacity)))
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middle_capacity = (min_capacity + max_capacity)
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>> (SCHED_CAPACITY_SHIFT+1);
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else
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middle_capacity = ((max_capacity / 3)
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>> (SCHED_CAPACITY_SHIFT-1)) + 1;
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if (cap_from_dt)
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topology_normalize_cpu_scale();
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}
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/*
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* Look for a customed capacity of a CPU in the cpu_capacity table during the
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* boot. The update of all CPUs is in O(n^2) for heteregeneous system but the
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* function returns directly for SMP system.
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*/
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static void update_cpu_capacity(unsigned int cpu)
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{
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if (!cpu_capacity(cpu) || cap_from_dt)
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return;
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topology_set_cpu_scale(cpu, cpu_capacity(cpu) / middle_capacity);
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pr_info("CPU%u: update cpu_capacity %lu\n",
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cpu, topology_get_cpu_scale(cpu));
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}
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#else
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static inline void parse_dt_topology(void) {}
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static inline void update_cpu_capacity(unsigned int cpuid) {}
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#endif
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/*
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* The current assumption is that we can power gate each core independently.
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* This will be superseded by DT binding once available.
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*/
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const struct cpumask *cpu_corepower_mask(int cpu)
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{
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return &cpu_topology[cpu].thread_sibling;
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}
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/*
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* store_cpu_topology is called at boot when only one cpu is running
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* and with the mutex cpu_hotplug.lock locked, when several cpus have booted,
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* which prevents simultaneous write access to cpu_topology array
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*/
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void store_cpu_topology(unsigned int cpuid)
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{
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struct cpu_topology *cpuid_topo = &cpu_topology[cpuid];
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unsigned int mpidr;
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/* If the cpu topology has been already set, just return */
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if (cpuid_topo->core_id != -1)
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return;
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mpidr = read_cpuid_mpidr();
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/* create cpu topology mapping */
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if ((mpidr & MPIDR_SMP_BITMASK) == MPIDR_SMP_VALUE) {
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/*
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* This is a multiprocessor system
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* multiprocessor format & multiprocessor mode field are set
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*/
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if (mpidr & MPIDR_MT_BITMASK) {
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/* core performance interdependency */
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cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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cpuid_topo->package_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
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} else {
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/* largely independent cores */
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cpuid_topo->thread_id = -1;
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cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cpuid_topo->package_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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}
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} else {
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/*
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* This is an uniprocessor system
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* we are in multiprocessor format but uniprocessor system
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* or in the old uniprocessor format
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*/
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cpuid_topo->thread_id = -1;
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cpuid_topo->core_id = 0;
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cpuid_topo->package_id = -1;
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}
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update_siblings_masks(cpuid);
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update_cpu_capacity(cpuid);
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pr_info("CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n",
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cpuid, cpu_topology[cpuid].thread_id,
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cpu_topology[cpuid].core_id,
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cpu_topology[cpuid].package_id, mpidr);
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}
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static inline int cpu_corepower_flags(void)
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{
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return SD_SHARE_PKG_RESOURCES | SD_SHARE_POWERDOMAIN;
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}
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static struct sched_domain_topology_level arm_topology[] = {
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#ifdef CONFIG_SCHED_MC
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{ cpu_corepower_mask, cpu_corepower_flags, SD_INIT_NAME(GMC) },
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{ cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
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#endif
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{ cpu_cpu_mask, SD_INIT_NAME(DIE) },
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{ NULL, },
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};
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/*
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* init_cpu_topology is called at boot when only one cpu is running
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* which prevent simultaneous write access to cpu_topology array
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*/
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void __init init_cpu_topology(void)
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{
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reset_cpu_topology();
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smp_wmb();
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parse_dt_topology();
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/* Set scheduler topology descriptor */
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set_sched_topology(arm_topology);
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}
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