mirror of https://gitee.com/openkylin/linux.git
211 lines
6.4 KiB
C
211 lines
6.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP.
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*
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H
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#define __DT_BINDINGS_CLOCK_IMX6SLL_H
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#define IMX6SLL_CLK_DUMMY 0
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#define IMX6SLL_CLK_CKIL 1
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#define IMX6SLL_CLK_OSC 2
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#define IMX6SLL_PLL1_BYPASS_SRC 3
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#define IMX6SLL_PLL2_BYPASS_SRC 4
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#define IMX6SLL_PLL3_BYPASS_SRC 5
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#define IMX6SLL_PLL4_BYPASS_SRC 6
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#define IMX6SLL_PLL5_BYPASS_SRC 7
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#define IMX6SLL_PLL6_BYPASS_SRC 8
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#define IMX6SLL_PLL7_BYPASS_SRC 9
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#define IMX6SLL_CLK_PLL1 10
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#define IMX6SLL_CLK_PLL2 11
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#define IMX6SLL_CLK_PLL3 12
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#define IMX6SLL_CLK_PLL4 13
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#define IMX6SLL_CLK_PLL5 14
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#define IMX6SLL_CLK_PLL6 15
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#define IMX6SLL_CLK_PLL7 16
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#define IMX6SLL_PLL1_BYPASS 17
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#define IMX6SLL_PLL2_BYPASS 18
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#define IMX6SLL_PLL3_BYPASS 19
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#define IMX6SLL_PLL4_BYPASS 20
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#define IMX6SLL_PLL5_BYPASS 21
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#define IMX6SLL_PLL6_BYPASS 22
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#define IMX6SLL_PLL7_BYPASS 23
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#define IMX6SLL_CLK_PLL1_SYS 24
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#define IMX6SLL_CLK_PLL2_BUS 25
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#define IMX6SLL_CLK_PLL3_USB_OTG 26
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#define IMX6SLL_CLK_PLL4_AUDIO 27
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#define IMX6SLL_CLK_PLL5_VIDEO 28
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#define IMX6SLL_CLK_PLL6_ENET 29
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#define IMX6SLL_CLK_PLL7_USB_HOST 30
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#define IMX6SLL_CLK_USBPHY1 31
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#define IMX6SLL_CLK_USBPHY2 32
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#define IMX6SLL_CLK_USBPHY1_GATE 33
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#define IMX6SLL_CLK_USBPHY2_GATE 34
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#define IMX6SLL_CLK_PLL2_PFD0 35
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#define IMX6SLL_CLK_PLL2_PFD1 36
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#define IMX6SLL_CLK_PLL2_PFD2 37
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#define IMX6SLL_CLK_PLL2_PFD3 38
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#define IMX6SLL_CLK_PLL3_PFD0 39
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#define IMX6SLL_CLK_PLL3_PFD1 40
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#define IMX6SLL_CLK_PLL3_PFD2 41
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#define IMX6SLL_CLK_PLL3_PFD3 42
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#define IMX6SLL_CLK_PLL4_POST_DIV 43
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#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44
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#define IMX6SLL_CLK_PLL5_POST_DIV 45
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#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46
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#define IMX6SLL_CLK_PLL2_198M 47
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#define IMX6SLL_CLK_PLL3_120M 48
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#define IMX6SLL_CLK_PLL3_80M 49
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#define IMX6SLL_CLK_PLL3_60M 50
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#define IMX6SLL_CLK_STEP 51
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#define IMX6SLL_CLK_PLL1_SW 52
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#define IMX6SLL_CLK_AXI_ALT_SEL 53
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#define IMX6SLL_CLK_AXI_SEL 54
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#define IMX6SLL_CLK_PERIPH_PRE 55
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#define IMX6SLL_CLK_PERIPH2_PRE 56
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#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57
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#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58
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#define IMX6SLL_CLK_PERCLK_SEL 59
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#define IMX6SLL_CLK_USDHC1_SEL 60
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#define IMX6SLL_CLK_USDHC2_SEL 61
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#define IMX6SLL_CLK_USDHC3_SEL 62
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#define IMX6SLL_CLK_SSI1_SEL 63
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#define IMX6SLL_CLK_SSI2_SEL 64
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#define IMX6SLL_CLK_SSI3_SEL 65
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#define IMX6SLL_CLK_PXP_SEL 66
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#define IMX6SLL_CLK_LCDIF_PRE_SEL 67
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#define IMX6SLL_CLK_LCDIF_SEL 68
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#define IMX6SLL_CLK_EPDC_PRE_SEL 69
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#define IMX6SLL_CLK_SPDIF_SEL 70
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#define IMX6SLL_CLK_ECSPI_SEL 71
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#define IMX6SLL_CLK_UART_SEL 72
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#define IMX6SLL_CLK_ARM 73
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#define IMX6SLL_CLK_PERIPH 74
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#define IMX6SLL_CLK_PERIPH2 75
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#define IMX6SLL_CLK_PERIPH2_CLK2 76
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#define IMX6SLL_CLK_PERIPH_CLK2 77
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#define IMX6SLL_CLK_MMDC_PODF 78
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#define IMX6SLL_CLK_AXI_PODF 79
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#define IMX6SLL_CLK_AHB 80
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#define IMX6SLL_CLK_IPG 81
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#define IMX6SLL_CLK_PERCLK 82
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#define IMX6SLL_CLK_USDHC1_PODF 83
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#define IMX6SLL_CLK_USDHC2_PODF 84
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#define IMX6SLL_CLK_USDHC3_PODF 85
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#define IMX6SLL_CLK_SSI1_PRED 86
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#define IMX6SLL_CLK_SSI2_PRED 87
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#define IMX6SLL_CLK_SSI3_PRED 88
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#define IMX6SLL_CLK_SSI1_PODF 89
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#define IMX6SLL_CLK_SSI2_PODF 90
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#define IMX6SLL_CLK_SSI3_PODF 91
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#define IMX6SLL_CLK_PXP_PODF 92
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#define IMX6SLL_CLK_LCDIF_PRED 93
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#define IMX6SLL_CLK_LCDIF_PODF 94
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#define IMX6SLL_CLK_EPDC_SEL 95
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#define IMX6SLL_CLK_EPDC_PODF 96
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#define IMX6SLL_CLK_SPDIF_PRED 97
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#define IMX6SLL_CLK_SPDIF_PODF 98
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#define IMX6SLL_CLK_ECSPI_PODF 99
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#define IMX6SLL_CLK_UART_PODF 100
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/* CCGR 0 */
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#define IMX6SLL_CLK_AIPSTZ1 101
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#define IMX6SLL_CLK_AIPSTZ2 102
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#define IMX6SLL_CLK_DCP 103
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#define IMX6SLL_CLK_UART2_IPG 104
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#define IMX6SLL_CLK_UART2_SERIAL 105
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/* CCGR 1 */
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#define IMX6SLL_CLK_ECSPI1 106
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#define IMX6SLL_CLK_ECSPI2 107
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#define IMX6SLL_CLK_ECSPI3 108
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#define IMX6SLL_CLK_ECSPI4 109
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#define IMX6SLL_CLK_UART3_IPG 110
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#define IMX6SLL_CLK_UART3_SERIAL 111
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#define IMX6SLL_CLK_UART4_IPG 112
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#define IMX6SLL_CLK_UART4_SERIAL 113
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#define IMX6SLL_CLK_EPIT1 114
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#define IMX6SLL_CLK_EPIT2 115
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#define IMX6SLL_CLK_GPT_BUS 116
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#define IMX6SLL_CLK_GPT_SERIAL 117
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/* CCGR2 */
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#define IMX6SLL_CLK_CSI 118
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#define IMX6SLL_CLK_I2C1 119
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#define IMX6SLL_CLK_I2C2 120
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#define IMX6SLL_CLK_I2C3 121
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#define IMX6SLL_CLK_OCOTP 122
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#define IMX6SLL_CLK_LCDIF_APB 123
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#define IMX6SLL_CLK_PXP 124
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/* CCGR3 */
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#define IMX6SLL_CLK_UART5_IPG 125
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#define IMX6SLL_CLK_UART5_SERIAL 126
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#define IMX6SLL_CLK_EPDC_AXI 127
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#define IMX6SLL_CLK_EPDC_PIX 128
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#define IMX6SLL_CLK_LCDIF_PIX 129
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#define IMX6SLL_CLK_WDOG1 130
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#define IMX6SLL_CLK_MMDC_P0_FAST 131
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#define IMX6SLL_CLK_MMDC_P0_IPG 132
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#define IMX6SLL_CLK_OCRAM 133
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/* CCGR4 */
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#define IMX6SLL_CLK_PWM1 134
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#define IMX6SLL_CLK_PWM2 135
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#define IMX6SLL_CLK_PWM3 136
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#define IMX6SLL_CLK_PWM4 137
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/* CCGR 5 */
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#define IMX6SLL_CLK_ROM 138
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#define IMX6SLL_CLK_SDMA 139
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#define IMX6SLL_CLK_KPP 140
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#define IMX6SLL_CLK_WDOG2 141
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#define IMX6SLL_CLK_SPBA 142
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#define IMX6SLL_CLK_SPDIF 143
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#define IMX6SLL_CLK_SPDIF_GCLK 144
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#define IMX6SLL_CLK_SSI1 145
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#define IMX6SLL_CLK_SSI1_IPG 146
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#define IMX6SLL_CLK_SSI2 147
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#define IMX6SLL_CLK_SSI2_IPG 148
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#define IMX6SLL_CLK_SSI3 149
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#define IMX6SLL_CLK_SSI3_IPG 150
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#define IMX6SLL_CLK_UART1_IPG 151
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#define IMX6SLL_CLK_UART1_SERIAL 152
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/* CCGR 6 */
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#define IMX6SLL_CLK_USBOH3 153
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#define IMX6SLL_CLK_USDHC1 154
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#define IMX6SLL_CLK_USDHC2 155
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#define IMX6SLL_CLK_USDHC3 156
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#define IMX6SLL_CLK_IPP_DI0 157
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#define IMX6SLL_CLK_IPP_DI1 158
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#define IMX6SLL_CLK_LDB_DI0_SEL 159
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#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160
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#define IMX6SLL_CLK_LDB_DI0_DIV_7 161
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#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162
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#define IMX6SLL_CLK_LDB_DI0 163
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#define IMX6SLL_CLK_LDB_DI1_SEL 164
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#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165
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#define IMX6SLL_CLK_LDB_DI1_DIV_7 166
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#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167
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#define IMX6SLL_CLK_LDB_DI1 168
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#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169
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#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170
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#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171
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#define IMX6SLL_CLK_EXTERN_AUDIO 172
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#define IMX6SLL_CLK_GPIO1 173
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#define IMX6SLL_CLK_GPIO2 174
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#define IMX6SLL_CLK_GPIO3 175
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#define IMX6SLL_CLK_GPIO4 176
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#define IMX6SLL_CLK_GPIO5 177
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#define IMX6SLL_CLK_GPIO6 178
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#define IMX6SLL_CLK_MMDC_P1_IPG 179
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#define IMX6SLL_CLK_END 180
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#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */
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