mirror of https://gitee.com/openkylin/linux.git
468 lines
12 KiB
C
468 lines
12 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2009-2013 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#include "../wifi.h"
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#include "reg.h"
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#include "def.h"
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#include "phy.h"
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#include "rf.h"
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#include "dm.h"
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void rtl88e_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_phy *rtlphy = &(rtlpriv->phy);
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switch (bandwidth) {
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case HT_CHANNEL_WIDTH_20:
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rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
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0xfffff3ff) | BIT(10) | BIT(11));
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rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
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rtlphy->rfreg_chnlval[0]);
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break;
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case HT_CHANNEL_WIDTH_20_40:
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rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
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0xfffff3ff) | BIT(10));
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rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
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rtlphy->rfreg_chnlval[0]);
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break;
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default:
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RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
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"unknown bandwidth: %#X\n", bandwidth);
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break;
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}
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}
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void rtl88e_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
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u8 *plevel)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_phy *rtlphy = &(rtlpriv->phy);
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struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
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struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
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u32 tx_agc[2] = {0, 0}, tmpval;
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bool turbo_scanoff = false;
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u8 idx1, idx2;
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u8 *ptr;
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u8 direction;
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u32 pwrtrac_value;
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if (rtlefuse->eeprom_regulatory != 0)
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turbo_scanoff = true;
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if (mac->act_scanning == true) {
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tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
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tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
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if (turbo_scanoff) {
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for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
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tx_agc[idx1] = plevel[idx1] |
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(plevel[idx1] << 8) |
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(plevel[idx1] << 16) |
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(plevel[idx1] << 24);
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}
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}
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} else {
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for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
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tx_agc[idx1] = plevel[idx1] | (plevel[idx1] << 8) |
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(plevel[idx1] << 16) |
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(plevel[idx1] << 24);
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}
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if (rtlefuse->eeprom_regulatory == 0) {
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tmpval = (rtlphy->mcs_offset[0][6]) +
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(rtlphy->mcs_offset[0][7] << 8);
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tx_agc[RF90_PATH_A] += tmpval;
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tmpval = (rtlphy->mcs_offset[0][14]) +
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(rtlphy->mcs_offset[0][15] << 24);
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tx_agc[RF90_PATH_B] += tmpval;
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}
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}
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for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
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ptr = (u8 *)(&(tx_agc[idx1]));
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for (idx2 = 0; idx2 < 4; idx2++) {
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if (*ptr > RF6052_MAX_TX_PWR)
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*ptr = RF6052_MAX_TX_PWR;
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ptr++;
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}
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}
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rtl88e_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
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if (direction == 1) {
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tx_agc[0] += pwrtrac_value;
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tx_agc[1] += pwrtrac_value;
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} else if (direction == 2) {
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tx_agc[0] -= pwrtrac_value;
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tx_agc[1] -= pwrtrac_value;
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}
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tmpval = tx_agc[RF90_PATH_A] & 0xff;
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rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
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"CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
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RTXAGC_A_CCK1_MCS32);
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tmpval = tx_agc[RF90_PATH_A] >> 8;
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rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
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"CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
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RTXAGC_B_CCK11_A_CCK2_11);
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tmpval = tx_agc[RF90_PATH_B] >> 24;
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rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
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"CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
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RTXAGC_B_CCK11_A_CCK2_11);
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tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
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rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
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"CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
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RTXAGC_B_CCK1_55_MCS32);
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}
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static void rtl88e_phy_get_power_base(struct ieee80211_hw *hw,
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u8 *pwrlvlofdm, u8 *pwrlvlbw20,
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u8 *pwrlvlbw40, u8 channel,
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u32 *ofdmbase, u32 *mcsbase)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_phy *rtlphy = &(rtlpriv->phy);
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u32 base0, base1;
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u8 i, powerlevel[2];
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for (i = 0; i < 2; i++) {
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base0 = pwrlvlofdm[i];
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base0 = (base0 << 24) | (base0 << 16) |
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(base0 << 8) | base0;
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*(ofdmbase + i) = base0;
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
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"[OFDM power base index rf(%c) = 0x%x]\n",
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((i == 0) ? 'A' : 'B'), *(ofdmbase + i));
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}
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for (i = 0; i < 2; i++) {
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if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
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powerlevel[i] = pwrlvlbw20[i];
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else
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powerlevel[i] = pwrlvlbw40[i];
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base1 = powerlevel[i];
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base1 = (base1 << 24) |
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(base1 << 16) | (base1 << 8) | base1;
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*(mcsbase + i) = base1;
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
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"[MCS power base index rf(%c) = 0x%x]\n",
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((i == 0) ? 'A' : 'B'), *(mcsbase + i));
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}
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}
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static void get_txpwr_by_reg(struct ieee80211_hw *hw, u8 chan, u8 index,
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u32 *base0, u32 *base1, u32 *outval)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_phy *rtlphy = &(rtlpriv->phy);
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struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
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u8 i, chg = 0, pwr_lim[4], pwr_diff = 0, cust_pwr_dif;
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u32 writeval, cust_lim, rf, tmp;
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u8 ch = chan - 1;
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u8 j;
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for (rf = 0; rf < 2; rf++) {
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j = index + (rf ? 8 : 0);
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tmp = ((index < 2) ? base0[rf] : base1[rf]);
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switch (rtlefuse->eeprom_regulatory) {
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case 0:
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chg = 0;
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writeval = rtlphy->mcs_offset[chg][j] + tmp;
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
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"RTK better performance, "
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"writeval(%c) = 0x%x\n",
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((rf == 0) ? 'A' : 'B'), writeval);
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break;
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case 1:
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if (rtlphy->pwrgroup_cnt == 1) {
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chg = 0;
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} else {
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chg = chan / 3;
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if (chan == 14)
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chg = 5;
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}
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writeval = rtlphy->mcs_offset[chg][j] + tmp;
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
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"Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
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((rf == 0) ? 'A' : 'B'), writeval);
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break;
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case 2:
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writeval = ((index < 2) ? base0[rf] : base1[rf]);
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
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"Better regulatory, writeval(%c) = 0x%x\n",
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((rf == 0) ? 'A' : 'B'), writeval);
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break;
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case 3:
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chg = 0;
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if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
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"customer's limit, 40MHz rf(%c) = 0x%x\n",
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((rf == 0) ? 'A' : 'B'),
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rtlefuse->pwrgroup_ht40[rf][ch]);
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} else {
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
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"customer's limit, 20MHz rf(%c) = 0x%x\n",
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((rf == 0) ? 'A' : 'B'),
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rtlefuse->pwrgroup_ht20[rf][ch]);
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}
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if (index < 2)
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pwr_diff = rtlefuse->txpwr_legacyhtdiff[rf][ch];
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else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
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pwr_diff = rtlefuse->txpwr_ht20diff[rf][ch];
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if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40)
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cust_pwr_dif = rtlefuse->pwrgroup_ht40[rf][ch];
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else
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cust_pwr_dif = rtlefuse->pwrgroup_ht20[rf][ch];
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if (pwr_diff > cust_pwr_dif)
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pwr_diff = 0;
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else
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pwr_diff = cust_pwr_dif - pwr_diff;
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for (i = 0; i < 4; i++) {
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pwr_lim[i] = (u8)((rtlphy->mcs_offset[chg][j] &
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(0x7f << (i * 8))) >> (i * 8));
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if (pwr_lim[i] > pwr_diff)
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pwr_lim[i] = pwr_diff;
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}
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cust_lim = (pwr_lim[3] << 24) | (pwr_lim[2] << 16) |
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(pwr_lim[1] << 8) | (pwr_lim[0]);
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
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"Customer's limit rf(%c) = 0x%x\n",
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((rf == 0) ? 'A' : 'B'), cust_lim);
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writeval = cust_lim + tmp;
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
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"Customer, writeval rf(%c) = 0x%x\n",
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((rf == 0) ? 'A' : 'B'), writeval);
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break;
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default:
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chg = 0;
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writeval = rtlphy->mcs_offset[chg][j] + tmp;
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
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"RTK better performance, writeval "
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"rf(%c) = 0x%x\n",
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((rf == 0) ? 'A' : 'B'), writeval);
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break;
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}
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if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
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writeval = writeval - 0x06060606;
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else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
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TXHIGHPWRLEVEL_BT2)
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writeval -= 0x0c0c0c0c;
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*(outval + rf) = writeval;
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}
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}
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static void write_ofdm_pwr(struct ieee80211_hw *hw, u8 index, u32 *pvalue)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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u16 regoffset_a[6] = {
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RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
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RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
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RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
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};
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u16 regoffset_b[6] = {
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RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
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RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
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RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
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};
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u8 i, rf, pwr_val[4];
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u32 writeval;
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u16 regoffset;
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for (rf = 0; rf < 2; rf++) {
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writeval = pvalue[rf];
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for (i = 0; i < 4; i++) {
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pwr_val[i] = (u8) ((writeval & (0x7f <<
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(i * 8))) >> (i * 8));
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if (pwr_val[i] > RF6052_MAX_TX_PWR)
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pwr_val[i] = RF6052_MAX_TX_PWR;
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}
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writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
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(pwr_val[1] << 8) | pwr_val[0];
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if (rf == 0)
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regoffset = regoffset_a[index];
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else
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regoffset = regoffset_b[index];
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rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval);
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RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
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"Set 0x%x = %08x\n", regoffset, writeval);
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}
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}
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void rtl88e_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
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u8 *pwrlvlofdm,
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u8 *pwrlvlbw20,
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u8 *pwrlvlbw40, u8 chan)
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{
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u32 writeval[2], base0[2], base1[2];
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u8 index;
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u8 direction;
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u32 pwrtrac_value;
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rtl88e_phy_get_power_base(hw, pwrlvlofdm, pwrlvlbw20,
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pwrlvlbw40, chan, &base0[0],
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&base1[0]);
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rtl88e_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
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for (index = 0; index < 6; index++) {
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get_txpwr_by_reg(hw, chan, index, &base0[0], &base1[0],
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&writeval[0]);
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if (direction == 1) {
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writeval[0] += pwrtrac_value;
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writeval[1] += pwrtrac_value;
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} else if (direction == 2) {
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writeval[0] -= pwrtrac_value;
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writeval[1] -= pwrtrac_value;
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}
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write_ofdm_pwr(hw, index, &writeval[0]);
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}
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}
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static bool rf6052_conf_para(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_phy *rtlphy = &(rtlpriv->phy);
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u32 u4val = 0;
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u8 rfpath;
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bool rtstatus = true;
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struct bb_reg_def *pphyreg;
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for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
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pphyreg = &rtlphy->phyreg_def[rfpath];
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switch (rfpath) {
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case RF90_PATH_A:
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case RF90_PATH_C:
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u4val = rtl_get_bbreg(hw, pphyreg->rfintfs,
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BRFSI_RFENV);
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break;
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case RF90_PATH_B:
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case RF90_PATH_D:
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u4val = rtl_get_bbreg(hw, pphyreg->rfintfs,
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BRFSI_RFENV << 16);
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break;
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}
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rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
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udelay(1);
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rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
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udelay(1);
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rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
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B3WIREADDREAALENGTH, 0x0);
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udelay(1);
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rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
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udelay(1);
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switch (rfpath) {
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case RF90_PATH_A:
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rtstatus = rtl88e_phy_config_rf_with_headerfile(hw,
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(enum radio_path)rfpath);
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break;
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case RF90_PATH_B:
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rtstatus = rtl88e_phy_config_rf_with_headerfile(hw,
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(enum radio_path)rfpath);
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break;
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case RF90_PATH_C:
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break;
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case RF90_PATH_D:
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break;
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}
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switch (rfpath) {
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case RF90_PATH_A:
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case RF90_PATH_C:
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rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, u4val);
|
|
break;
|
|
case RF90_PATH_B:
|
|
case RF90_PATH_D:
|
|
rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
|
|
u4val);
|
|
break;
|
|
}
|
|
|
|
if (rtstatus != true) {
|
|
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
|
|
"Radio[%d] Fail!!", rfpath);
|
|
return false;
|
|
}
|
|
}
|
|
|
|
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
|
|
return rtstatus;
|
|
}
|
|
|
|
bool rtl88e_phy_rf6052_config(struct ieee80211_hw *hw)
|
|
{
|
|
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
|
struct rtl_phy *rtlphy = &(rtlpriv->phy);
|
|
|
|
if (rtlphy->rf_type == RF_1T1R)
|
|
rtlphy->num_total_rfpath = 1;
|
|
else
|
|
rtlphy->num_total_rfpath = 2;
|
|
|
|
return rf6052_conf_para(hw);
|
|
}
|