mirror of https://gitee.com/openkylin/linux.git
593 lines
14 KiB
C
593 lines
14 KiB
C
/*
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* Versatile Express Serial Power Controller (SPC) support
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*
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* Copyright (C) 2013 ARM Ltd.
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*
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* Authors: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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* Achin Gupta <achin.gupta@arm.com>
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* Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/cpu.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/slab.h>
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#include <linux/semaphore.h>
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#include <asm/cacheflush.h>
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#define SPCLOG "vexpress-spc: "
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#define PERF_LVL_A15 0x00
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#define PERF_REQ_A15 0x04
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#define PERF_LVL_A7 0x08
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#define PERF_REQ_A7 0x0c
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#define COMMS 0x10
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#define COMMS_REQ 0x14
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#define PWC_STATUS 0x18
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#define PWC_FLAG 0x1c
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/* SPC wake-up IRQs status and mask */
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#define WAKE_INT_MASK 0x24
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#define WAKE_INT_RAW 0x28
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#define WAKE_INT_STAT 0x2c
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/* SPC power down registers */
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#define A15_PWRDN_EN 0x30
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#define A7_PWRDN_EN 0x34
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/* SPC per-CPU mailboxes */
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#define A15_BX_ADDR0 0x68
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#define A7_BX_ADDR0 0x78
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/* SPC CPU/cluster reset statue */
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#define STANDBYWFI_STAT 0x3c
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#define STANDBYWFI_STAT_A15_CPU_MASK(cpu) (1 << (cpu))
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#define STANDBYWFI_STAT_A7_CPU_MASK(cpu) (1 << (3 + (cpu)))
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/* SPC system config interface registers */
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#define SYSCFG_WDATA 0x70
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#define SYSCFG_RDATA 0x74
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/* A15/A7 OPP virtual register base */
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#define A15_PERFVAL_BASE 0xC10
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#define A7_PERFVAL_BASE 0xC30
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/* Config interface control bits */
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#define SYSCFG_START (1 << 31)
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#define SYSCFG_SCC (6 << 20)
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#define SYSCFG_STAT (14 << 20)
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/* wake-up interrupt masks */
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#define GBL_WAKEUP_INT_MSK (0x3 << 10)
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/* TC2 static dual-cluster configuration */
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#define MAX_CLUSTERS 2
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/*
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* Even though the SPC takes max 3-5 ms to complete any OPP/COMMS
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* operation, the operation could start just before jiffie is about
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* to be incremented. So setting timeout value of 20ms = 2jiffies@100Hz
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*/
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#define TIMEOUT_US 20000
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#define MAX_OPPS 8
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#define CA15_DVFS 0
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#define CA7_DVFS 1
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#define SPC_SYS_CFG 2
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#define STAT_COMPLETE(type) ((1 << 0) << (type << 2))
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#define STAT_ERR(type) ((1 << 1) << (type << 2))
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#define RESPONSE_MASK(type) (STAT_COMPLETE(type) | STAT_ERR(type))
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struct ve_spc_opp {
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unsigned long freq;
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unsigned long u_volt;
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};
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struct ve_spc_drvdata {
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void __iomem *baseaddr;
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/*
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* A15s cluster identifier
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* It corresponds to A15 processors MPIDR[15:8] bitfield
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*/
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u32 a15_clusid;
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uint32_t cur_rsp_mask;
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uint32_t cur_rsp_stat;
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struct semaphore sem;
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struct completion done;
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struct ve_spc_opp *opps[MAX_CLUSTERS];
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int num_opps[MAX_CLUSTERS];
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};
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static struct ve_spc_drvdata *info;
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static inline bool cluster_is_a15(u32 cluster)
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{
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return cluster == info->a15_clusid;
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}
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/**
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* ve_spc_global_wakeup_irq()
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*
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* Function to set/clear global wakeup IRQs. Not protected by locking since
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* it might be used in code paths where normal cacheable locks are not
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* working. Locking must be provided by the caller to ensure atomicity.
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*
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* @set: if true, global wake-up IRQs are set, if false they are cleared
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*/
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void ve_spc_global_wakeup_irq(bool set)
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{
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u32 reg;
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reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
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if (set)
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reg |= GBL_WAKEUP_INT_MSK;
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else
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reg &= ~GBL_WAKEUP_INT_MSK;
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writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
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}
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/**
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* ve_spc_cpu_wakeup_irq()
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*
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* Function to set/clear per-CPU wake-up IRQs. Not protected by locking since
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* it might be used in code paths where normal cacheable locks are not
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* working. Locking must be provided by the caller to ensure atomicity.
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*
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* @cluster: mpidr[15:8] bitfield describing cluster affinity level
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* @cpu: mpidr[7:0] bitfield describing cpu affinity level
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* @set: if true, wake-up IRQs are set, if false they are cleared
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*/
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void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set)
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{
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u32 mask, reg;
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if (cluster >= MAX_CLUSTERS)
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return;
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mask = 1 << cpu;
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if (!cluster_is_a15(cluster))
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mask <<= 4;
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reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
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if (set)
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reg |= mask;
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else
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reg &= ~mask;
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writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
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}
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/**
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* ve_spc_set_resume_addr() - set the jump address used for warm boot
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*
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* @cluster: mpidr[15:8] bitfield describing cluster affinity level
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* @cpu: mpidr[7:0] bitfield describing cpu affinity level
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* @addr: physical resume address
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*/
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void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr)
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{
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void __iomem *baseaddr;
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if (cluster >= MAX_CLUSTERS)
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return;
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if (cluster_is_a15(cluster))
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baseaddr = info->baseaddr + A15_BX_ADDR0 + (cpu << 2);
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else
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baseaddr = info->baseaddr + A7_BX_ADDR0 + (cpu << 2);
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writel_relaxed(addr, baseaddr);
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}
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/**
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* ve_spc_powerdown()
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*
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* Function to enable/disable cluster powerdown. Not protected by locking
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* since it might be used in code paths where normal cacheable locks are not
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* working. Locking must be provided by the caller to ensure atomicity.
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*
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* @cluster: mpidr[15:8] bitfield describing cluster affinity level
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* @enable: if true enables powerdown, if false disables it
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*/
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void ve_spc_powerdown(u32 cluster, bool enable)
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{
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u32 pwdrn_reg;
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if (cluster >= MAX_CLUSTERS)
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return;
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pwdrn_reg = cluster_is_a15(cluster) ? A15_PWRDN_EN : A7_PWRDN_EN;
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writel_relaxed(enable, info->baseaddr + pwdrn_reg);
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}
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static u32 standbywfi_cpu_mask(u32 cpu, u32 cluster)
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{
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return cluster_is_a15(cluster) ?
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STANDBYWFI_STAT_A15_CPU_MASK(cpu)
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: STANDBYWFI_STAT_A7_CPU_MASK(cpu);
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}
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/**
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* ve_spc_cpu_in_wfi(u32 cpu, u32 cluster)
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*
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* @cpu: mpidr[7:0] bitfield describing CPU affinity level within cluster
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* @cluster: mpidr[15:8] bitfield describing cluster affinity level
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*
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* @return: non-zero if and only if the specified CPU is in WFI
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*
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* Take care when interpreting the result of this function: a CPU might
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* be in WFI temporarily due to idle, and is not necessarily safely
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* parked.
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*/
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int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster)
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{
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int ret;
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u32 mask = standbywfi_cpu_mask(cpu, cluster);
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if (cluster >= MAX_CLUSTERS)
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return 1;
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ret = readl_relaxed(info->baseaddr + STANDBYWFI_STAT);
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pr_debug("%s: PCFGREG[0x%X] = 0x%08X, mask = 0x%X\n",
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__func__, STANDBYWFI_STAT, ret, mask);
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return ret & mask;
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}
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static int ve_spc_get_performance(int cluster, u32 *freq)
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{
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struct ve_spc_opp *opps = info->opps[cluster];
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u32 perf_cfg_reg = 0;
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u32 perf;
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perf_cfg_reg = cluster_is_a15(cluster) ? PERF_LVL_A15 : PERF_LVL_A7;
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perf = readl_relaxed(info->baseaddr + perf_cfg_reg);
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if (perf >= info->num_opps[cluster])
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return -EINVAL;
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opps += perf;
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*freq = opps->freq;
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return 0;
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}
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/* find closest match to given frequency in OPP table */
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static int ve_spc_round_performance(int cluster, u32 freq)
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{
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int idx, max_opp = info->num_opps[cluster];
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struct ve_spc_opp *opps = info->opps[cluster];
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u32 fmin = 0, fmax = ~0, ftmp;
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freq /= 1000; /* OPP entries in kHz */
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for (idx = 0; idx < max_opp; idx++, opps++) {
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ftmp = opps->freq;
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if (ftmp >= freq) {
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if (ftmp <= fmax)
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fmax = ftmp;
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} else {
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if (ftmp >= fmin)
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fmin = ftmp;
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}
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}
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if (fmax != ~0)
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return fmax * 1000;
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else
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return fmin * 1000;
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}
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static int ve_spc_find_performance_index(int cluster, u32 freq)
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{
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int idx, max_opp = info->num_opps[cluster];
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struct ve_spc_opp *opps = info->opps[cluster];
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for (idx = 0; idx < max_opp; idx++, opps++)
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if (opps->freq == freq)
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break;
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return (idx == max_opp) ? -EINVAL : idx;
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}
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static int ve_spc_waitforcompletion(int req_type)
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{
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int ret = wait_for_completion_interruptible_timeout(
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&info->done, usecs_to_jiffies(TIMEOUT_US));
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if (ret == 0)
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ret = -ETIMEDOUT;
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else if (ret > 0)
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ret = info->cur_rsp_stat & STAT_COMPLETE(req_type) ? 0 : -EIO;
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return ret;
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}
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static int ve_spc_set_performance(int cluster, u32 freq)
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{
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u32 perf_cfg_reg, perf_stat_reg;
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int ret, perf, req_type;
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if (cluster_is_a15(cluster)) {
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req_type = CA15_DVFS;
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perf_cfg_reg = PERF_LVL_A15;
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perf_stat_reg = PERF_REQ_A15;
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} else {
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req_type = CA7_DVFS;
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perf_cfg_reg = PERF_LVL_A7;
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perf_stat_reg = PERF_REQ_A7;
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}
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perf = ve_spc_find_performance_index(cluster, freq);
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if (perf < 0)
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return perf;
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if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US)))
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return -ETIME;
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init_completion(&info->done);
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info->cur_rsp_mask = RESPONSE_MASK(req_type);
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writel(perf, info->baseaddr + perf_cfg_reg);
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ret = ve_spc_waitforcompletion(req_type);
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info->cur_rsp_mask = 0;
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up(&info->sem);
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return ret;
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}
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static int ve_spc_read_sys_cfg(int func, int offset, uint32_t *data)
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{
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int ret;
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if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US)))
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return -ETIME;
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init_completion(&info->done);
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info->cur_rsp_mask = RESPONSE_MASK(SPC_SYS_CFG);
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/* Set the control value */
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writel(SYSCFG_START | func | offset >> 2, info->baseaddr + COMMS);
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ret = ve_spc_waitforcompletion(SPC_SYS_CFG);
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if (ret == 0)
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*data = readl(info->baseaddr + SYSCFG_RDATA);
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info->cur_rsp_mask = 0;
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up(&info->sem);
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return ret;
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}
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static irqreturn_t ve_spc_irq_handler(int irq, void *data)
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{
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struct ve_spc_drvdata *drv_data = data;
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uint32_t status = readl_relaxed(drv_data->baseaddr + PWC_STATUS);
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if (info->cur_rsp_mask & status) {
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info->cur_rsp_stat = status;
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complete(&drv_data->done);
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}
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return IRQ_HANDLED;
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}
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/*
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* +--------------------------+
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* | 31 20 | 19 0 |
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* +--------------------------+
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* | m_volt | freq(kHz) |
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* +--------------------------+
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*/
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#define MULT_FACTOR 20
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#define VOLT_SHIFT 20
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#define FREQ_MASK (0xFFFFF)
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static int ve_spc_populate_opps(uint32_t cluster)
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{
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uint32_t data = 0, off, ret, idx;
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struct ve_spc_opp *opps;
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opps = kzalloc(sizeof(*opps) * MAX_OPPS, GFP_KERNEL);
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if (!opps)
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return -ENOMEM;
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info->opps[cluster] = opps;
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off = cluster_is_a15(cluster) ? A15_PERFVAL_BASE : A7_PERFVAL_BASE;
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for (idx = 0; idx < MAX_OPPS; idx++, off += 4, opps++) {
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ret = ve_spc_read_sys_cfg(SYSCFG_SCC, off, &data);
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if (!ret) {
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opps->freq = (data & FREQ_MASK) * MULT_FACTOR;
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opps->u_volt = (data >> VOLT_SHIFT) * 1000;
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} else {
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break;
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}
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}
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info->num_opps[cluster] = idx;
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return ret;
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}
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static int ve_init_opp_table(struct device *cpu_dev)
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{
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int cluster;
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int idx, ret = 0, max_opp;
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struct ve_spc_opp *opps;
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cluster = topology_physical_package_id(cpu_dev->id);
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cluster = cluster < 0 ? 0 : cluster;
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max_opp = info->num_opps[cluster];
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opps = info->opps[cluster];
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for (idx = 0; idx < max_opp; idx++, opps++) {
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ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt);
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if (ret) {
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dev_warn(cpu_dev, "failed to add opp %lu %lu\n",
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opps->freq, opps->u_volt);
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return ret;
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}
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}
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return ret;
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}
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int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid, int irq)
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{
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int ret;
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info = kzalloc(sizeof(*info), GFP_KERNEL);
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if (!info) {
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pr_err(SPCLOG "unable to allocate mem\n");
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return -ENOMEM;
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}
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info->baseaddr = baseaddr;
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info->a15_clusid = a15_clusid;
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if (irq <= 0) {
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pr_err(SPCLOG "Invalid IRQ %d\n", irq);
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kfree(info);
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return -EINVAL;
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}
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init_completion(&info->done);
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readl_relaxed(info->baseaddr + PWC_STATUS);
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ret = request_irq(irq, ve_spc_irq_handler, IRQF_TRIGGER_HIGH
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| IRQF_ONESHOT, "vexpress-spc", info);
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if (ret) {
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pr_err(SPCLOG "IRQ %d request failed\n", irq);
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kfree(info);
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return -ENODEV;
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}
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sema_init(&info->sem, 1);
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/*
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* Multi-cluster systems may need this data when non-coherent, during
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* cluster power-up/power-down. Make sure driver info reaches main
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* memory.
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*/
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sync_cache_w(info);
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sync_cache_w(&info);
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return 0;
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}
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struct clk_spc {
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struct clk_hw hw;
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int cluster;
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};
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#define to_clk_spc(spc) container_of(spc, struct clk_spc, hw)
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static unsigned long spc_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_spc *spc = to_clk_spc(hw);
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u32 freq;
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if (ve_spc_get_performance(spc->cluster, &freq))
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return -EIO;
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return freq * 1000;
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}
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static long spc_round_rate(struct clk_hw *hw, unsigned long drate,
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unsigned long *parent_rate)
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{
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struct clk_spc *spc = to_clk_spc(hw);
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|
|
|
return ve_spc_round_performance(spc->cluster, drate);
|
|
}
|
|
|
|
static int spc_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct clk_spc *spc = to_clk_spc(hw);
|
|
|
|
return ve_spc_set_performance(spc->cluster, rate / 1000);
|
|
}
|
|
|
|
static struct clk_ops clk_spc_ops = {
|
|
.recalc_rate = spc_recalc_rate,
|
|
.round_rate = spc_round_rate,
|
|
.set_rate = spc_set_rate,
|
|
};
|
|
|
|
static struct clk *ve_spc_clk_register(struct device *cpu_dev)
|
|
{
|
|
struct clk_init_data init;
|
|
struct clk_spc *spc;
|
|
|
|
spc = kzalloc(sizeof(*spc), GFP_KERNEL);
|
|
if (!spc) {
|
|
pr_err("could not allocate spc clk\n");
|
|
return ERR_PTR(-ENOMEM);
|
|
}
|
|
|
|
spc->hw.init = &init;
|
|
spc->cluster = topology_physical_package_id(cpu_dev->id);
|
|
|
|
spc->cluster = spc->cluster < 0 ? 0 : spc->cluster;
|
|
|
|
init.name = dev_name(cpu_dev);
|
|
init.ops = &clk_spc_ops;
|
|
init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE;
|
|
init.num_parents = 0;
|
|
|
|
return devm_clk_register(cpu_dev, &spc->hw);
|
|
}
|
|
|
|
static int __init ve_spc_clk_init(void)
|
|
{
|
|
int cpu;
|
|
struct clk *clk;
|
|
|
|
if (!info)
|
|
return 0; /* Continue only if SPC is initialised */
|
|
|
|
if (ve_spc_populate_opps(0) || ve_spc_populate_opps(1)) {
|
|
pr_err("failed to build OPP table\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
struct device *cpu_dev = get_cpu_device(cpu);
|
|
if (!cpu_dev) {
|
|
pr_warn("failed to get cpu%d device\n", cpu);
|
|
continue;
|
|
}
|
|
clk = ve_spc_clk_register(cpu_dev);
|
|
if (IS_ERR(clk)) {
|
|
pr_warn("failed to register cpu%d clock\n", cpu);
|
|
continue;
|
|
}
|
|
if (clk_register_clkdev(clk, NULL, dev_name(cpu_dev))) {
|
|
pr_warn("failed to register cpu%d clock lookup\n", cpu);
|
|
continue;
|
|
}
|
|
|
|
if (ve_init_opp_table(cpu_dev))
|
|
pr_warn("failed to initialise cpu%d opp table\n", cpu);
|
|
}
|
|
|
|
platform_device_register_simple("vexpress-spc-cpufreq", -1, NULL, 0);
|
|
return 0;
|
|
}
|
|
module_init(ve_spc_clk_init);
|