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59 lines
2.0 KiB
Plaintext
59 lines
2.0 KiB
Plaintext
STMicroelectronics SoC DWMAC glue layer controller
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The device node has following properties.
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Required properties:
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- compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac" or
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"st,stid127-dwmac".
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- reg : Offset of the glue configuration register map in system
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configuration regmap pointed by st,syscon property and size.
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- reg-names : Should be "sti-ethconf".
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- st,syscon : Should be phandle to system configuration node which
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encompases this glue registers.
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- st,tx-retime-src: On STi Parts for Giga bit speeds, 125Mhz clocks can be
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wired up in from different sources. One via TXCLK pin and other via CLK_125
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pin. This wiring is totally board dependent. However the retiming glue
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logic should be configured accordingly. Possible values for this property
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"txclk" - if 125Mhz clock is wired up via txclk line.
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"clk_125" - if 125Mhz clock is wired up via clk_125 line.
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This property is only valid for Giga bit setup( GMII, RGMII), and it is
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un-used for non-giga bit (MII and RMII) setups. Also note that internal
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clockgen can not generate stable 125Mhz clock.
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- st,ext-phyclk: This boolean property indicates who is generating the clock
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for tx and rx. This property is only valid for RMII case where the clock can
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be generated from the MAC or PHY.
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- clock-names: should be "sti-ethclk".
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- clocks: Should point to ethernet clockgen which can generate phyclk.
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Example:
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ethernet0: dwmac@fe810000 {
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device_type = "network";
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compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
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reg = <0xfe810000 0x8000>, <0x8bc 0x4>;
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reg-names = "stmmaceth", "sti-ethconf";
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interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
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interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
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phy-mode = "mii";
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st,syscon = <&syscfg_rear>;
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snps,pbl = <32>;
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snps,mixed-burst;
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resets = <&softreset STIH416_ETH0_SOFTRESET>;
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reset-names = "stmmaceth";
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pinctrl-0 = <&pinctrl_mii0>;
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pinctrl-names = "default";
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clocks = <&CLK_S_GMAC0_PHY>;
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clock-names = "stmmaceth";
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};
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