mirror of https://gitee.com/openkylin/linux.git
707 lines
16 KiB
C
707 lines
16 KiB
C
/*
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* SuperH Timer Support - TMU
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*
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* Copyright (C) 2009 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_runtime.h>
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#include <linux/sh_timer.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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enum sh_tmu_model {
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SH_TMU_LEGACY,
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SH_TMU,
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SH_TMU_SH3,
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};
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struct sh_tmu_device;
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struct sh_tmu_channel {
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struct sh_tmu_device *tmu;
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unsigned int index;
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void __iomem *base;
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int irq;
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unsigned long rate;
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unsigned long periodic;
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struct clock_event_device ced;
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struct clocksource cs;
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bool cs_enabled;
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unsigned int enable_count;
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};
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struct sh_tmu_device {
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struct platform_device *pdev;
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void __iomem *mapbase;
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struct clk *clk;
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enum sh_tmu_model model;
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struct sh_tmu_channel *channels;
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unsigned int num_channels;
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bool has_clockevent;
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bool has_clocksource;
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};
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static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
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#define TSTR -1 /* shared register */
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#define TCOR 0 /* channel register */
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#define TCNT 1 /* channel register */
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#define TCR 2 /* channel register */
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#define TCR_UNF (1 << 8)
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#define TCR_UNIE (1 << 5)
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#define TCR_TPSC_CLK4 (0 << 0)
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#define TCR_TPSC_CLK16 (1 << 0)
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#define TCR_TPSC_CLK64 (2 << 0)
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#define TCR_TPSC_CLK256 (3 << 0)
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#define TCR_TPSC_CLK1024 (4 << 0)
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#define TCR_TPSC_MASK (7 << 0)
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static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
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{
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unsigned long offs;
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if (reg_nr == TSTR) {
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switch (ch->tmu->model) {
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case SH_TMU_LEGACY:
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return ioread8(ch->tmu->mapbase);
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case SH_TMU_SH3:
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return ioread8(ch->tmu->mapbase + 2);
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case SH_TMU:
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return ioread8(ch->tmu->mapbase + 4);
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}
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}
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offs = reg_nr << 2;
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if (reg_nr == TCR)
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return ioread16(ch->base + offs);
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else
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return ioread32(ch->base + offs);
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}
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static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,
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unsigned long value)
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{
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unsigned long offs;
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if (reg_nr == TSTR) {
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switch (ch->tmu->model) {
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case SH_TMU_LEGACY:
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return iowrite8(value, ch->tmu->mapbase);
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case SH_TMU_SH3:
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return iowrite8(value, ch->tmu->mapbase + 2);
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case SH_TMU:
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return iowrite8(value, ch->tmu->mapbase + 4);
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}
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}
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offs = reg_nr << 2;
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if (reg_nr == TCR)
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iowrite16(value, ch->base + offs);
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else
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iowrite32(value, ch->base + offs);
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}
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static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
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{
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unsigned long flags, value;
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/* start stop register shared by multiple timer channels */
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raw_spin_lock_irqsave(&sh_tmu_lock, flags);
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value = sh_tmu_read(ch, TSTR);
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if (start)
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value |= 1 << ch->index;
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else
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value &= ~(1 << ch->index);
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sh_tmu_write(ch, TSTR, value);
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raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
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}
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static int __sh_tmu_enable(struct sh_tmu_channel *ch)
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{
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int ret;
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/* enable clock */
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ret = clk_enable(ch->tmu->clk);
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if (ret) {
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dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",
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ch->index);
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return ret;
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}
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/* make sure channel is disabled */
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sh_tmu_start_stop_ch(ch, 0);
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/* maximum timeout */
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sh_tmu_write(ch, TCOR, 0xffffffff);
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sh_tmu_write(ch, TCNT, 0xffffffff);
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/* configure channel to parent clock / 4, irq off */
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ch->rate = clk_get_rate(ch->tmu->clk) / 4;
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sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
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/* enable channel */
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sh_tmu_start_stop_ch(ch, 1);
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return 0;
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}
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static int sh_tmu_enable(struct sh_tmu_channel *ch)
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{
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if (ch->enable_count++ > 0)
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return 0;
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pm_runtime_get_sync(&ch->tmu->pdev->dev);
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dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
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return __sh_tmu_enable(ch);
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}
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static void __sh_tmu_disable(struct sh_tmu_channel *ch)
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{
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/* disable channel */
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sh_tmu_start_stop_ch(ch, 0);
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/* disable interrupts in TMU block */
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sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
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/* stop clock */
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clk_disable(ch->tmu->clk);
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}
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static void sh_tmu_disable(struct sh_tmu_channel *ch)
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{
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if (WARN_ON(ch->enable_count == 0))
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return;
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if (--ch->enable_count > 0)
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return;
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__sh_tmu_disable(ch);
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dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
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pm_runtime_put(&ch->tmu->pdev->dev);
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}
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static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
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int periodic)
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{
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/* stop timer */
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sh_tmu_start_stop_ch(ch, 0);
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/* acknowledge interrupt */
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sh_tmu_read(ch, TCR);
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/* enable interrupt */
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sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
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/* reload delta value in case of periodic timer */
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if (periodic)
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sh_tmu_write(ch, TCOR, delta);
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else
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sh_tmu_write(ch, TCOR, 0xffffffff);
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sh_tmu_write(ch, TCNT, delta);
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/* start timer */
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sh_tmu_start_stop_ch(ch, 1);
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}
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static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
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{
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struct sh_tmu_channel *ch = dev_id;
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/* disable or acknowledge interrupt */
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if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT)
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sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
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else
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sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
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/* notify clockevent layer */
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ch->ced.event_handler(&ch->ced);
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return IRQ_HANDLED;
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}
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static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
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{
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return container_of(cs, struct sh_tmu_channel, cs);
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}
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static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
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{
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struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
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return sh_tmu_read(ch, TCNT) ^ 0xffffffff;
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}
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static int sh_tmu_clocksource_enable(struct clocksource *cs)
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{
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struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
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int ret;
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if (WARN_ON(ch->cs_enabled))
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return 0;
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ret = sh_tmu_enable(ch);
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if (!ret) {
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__clocksource_updatefreq_hz(cs, ch->rate);
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ch->cs_enabled = true;
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}
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return ret;
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}
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static void sh_tmu_clocksource_disable(struct clocksource *cs)
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{
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struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
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if (WARN_ON(!ch->cs_enabled))
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return;
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sh_tmu_disable(ch);
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ch->cs_enabled = false;
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}
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static void sh_tmu_clocksource_suspend(struct clocksource *cs)
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{
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struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
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if (!ch->cs_enabled)
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return;
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if (--ch->enable_count == 0) {
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__sh_tmu_disable(ch);
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pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev);
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}
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}
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static void sh_tmu_clocksource_resume(struct clocksource *cs)
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{
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struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
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if (!ch->cs_enabled)
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return;
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if (ch->enable_count++ == 0) {
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pm_genpd_syscore_poweron(&ch->tmu->pdev->dev);
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__sh_tmu_enable(ch);
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}
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}
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static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
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const char *name)
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{
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struct clocksource *cs = &ch->cs;
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cs->name = name;
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cs->rating = 200;
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cs->read = sh_tmu_clocksource_read;
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cs->enable = sh_tmu_clocksource_enable;
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cs->disable = sh_tmu_clocksource_disable;
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cs->suspend = sh_tmu_clocksource_suspend;
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cs->resume = sh_tmu_clocksource_resume;
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cs->mask = CLOCKSOURCE_MASK(32);
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cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
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dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",
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ch->index);
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/* Register with dummy 1 Hz value, gets updated in ->enable() */
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clocksource_register_hz(cs, 1);
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return 0;
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}
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static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
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{
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return container_of(ced, struct sh_tmu_channel, ced);
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}
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static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic)
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{
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struct clock_event_device *ced = &ch->ced;
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sh_tmu_enable(ch);
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clockevents_config(ced, ch->rate);
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if (periodic) {
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ch->periodic = (ch->rate + HZ/2) / HZ;
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sh_tmu_set_next(ch, ch->periodic, 1);
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}
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}
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static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
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struct clock_event_device *ced)
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{
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struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
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int disabled = 0;
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/* deal with old setting first */
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switch (ced->mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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case CLOCK_EVT_MODE_ONESHOT:
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sh_tmu_disable(ch);
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disabled = 1;
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break;
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default:
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break;
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}
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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dev_info(&ch->tmu->pdev->dev,
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"ch%u: used for periodic clock events\n", ch->index);
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sh_tmu_clock_event_start(ch, 1);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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dev_info(&ch->tmu->pdev->dev,
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"ch%u: used for oneshot clock events\n", ch->index);
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sh_tmu_clock_event_start(ch, 0);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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if (!disabled)
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sh_tmu_disable(ch);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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break;
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}
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}
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static int sh_tmu_clock_event_next(unsigned long delta,
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struct clock_event_device *ced)
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{
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struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
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BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
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/* program new delta value */
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sh_tmu_set_next(ch, delta, 0);
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return 0;
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}
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static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
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{
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pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
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}
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static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
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{
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pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
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}
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static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
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const char *name)
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{
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struct clock_event_device *ced = &ch->ced;
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int ret;
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ced->name = name;
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ced->features = CLOCK_EVT_FEAT_PERIODIC;
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ced->features |= CLOCK_EVT_FEAT_ONESHOT;
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ced->rating = 200;
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ced->cpumask = cpumask_of(0);
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ced->set_next_event = sh_tmu_clock_event_next;
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ced->set_mode = sh_tmu_clock_event_mode;
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ced->suspend = sh_tmu_clock_event_suspend;
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ced->resume = sh_tmu_clock_event_resume;
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dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n",
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ch->index);
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clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
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ret = request_irq(ch->irq, sh_tmu_interrupt,
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IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
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dev_name(&ch->tmu->pdev->dev), ch);
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if (ret) {
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dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n",
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ch->index, ch->irq);
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return;
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}
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}
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static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
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bool clockevent, bool clocksource)
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{
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if (clockevent) {
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ch->tmu->has_clockevent = true;
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sh_tmu_register_clockevent(ch, name);
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} else if (clocksource) {
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ch->tmu->has_clocksource = true;
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sh_tmu_register_clocksource(ch, name);
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}
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return 0;
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}
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static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
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bool clockevent, bool clocksource,
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struct sh_tmu_device *tmu)
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{
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/* Skip unused channels. */
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if (!clockevent && !clocksource)
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return 0;
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ch->tmu = tmu;
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if (tmu->model == SH_TMU_LEGACY) {
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struct sh_timer_config *cfg = tmu->pdev->dev.platform_data;
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/*
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* The SH3 variant (SH770x, SH7705, SH7710 and SH7720) maps
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* channel registers blocks at base + 2 + 12 * index, while all
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* other variants map them at base + 4 + 12 * index. We can
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* compute the index by just dividing by 12, the 2 bytes or 4
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* bytes offset being hidden by the integer division.
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*/
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ch->index = cfg->channel_offset / 12;
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ch->base = tmu->mapbase + cfg->channel_offset;
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} else {
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ch->index = index;
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if (tmu->model == SH_TMU_SH3)
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ch->base = tmu->mapbase + 4 + ch->index * 12;
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else
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ch->base = tmu->mapbase + 8 + ch->index * 12;
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}
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ch->irq = platform_get_irq(tmu->pdev, index);
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if (ch->irq < 0) {
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dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n",
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ch->index);
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return ch->irq;
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}
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ch->cs_enabled = false;
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ch->enable_count = 0;
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return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),
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clockevent, clocksource);
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}
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static int sh_tmu_map_memory(struct sh_tmu_device *tmu)
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{
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struct resource *res;
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res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
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return -ENXIO;
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}
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tmu->mapbase = ioremap_nocache(res->start, resource_size(res));
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if (tmu->mapbase == NULL)
|
|
return -ENXIO;
|
|
|
|
/*
|
|
* In legacy platform device configuration (with one device per channel)
|
|
* the resource points to the channel base address.
|
|
*/
|
|
if (tmu->model == SH_TMU_LEGACY) {
|
|
struct sh_timer_config *cfg = tmu->pdev->dev.platform_data;
|
|
tmu->mapbase -= cfg->channel_offset;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sh_tmu_unmap_memory(struct sh_tmu_device *tmu)
|
|
{
|
|
if (tmu->model == SH_TMU_LEGACY) {
|
|
struct sh_timer_config *cfg = tmu->pdev->dev.platform_data;
|
|
tmu->mapbase += cfg->channel_offset;
|
|
}
|
|
|
|
iounmap(tmu->mapbase);
|
|
}
|
|
|
|
static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
|
|
{
|
|
struct sh_timer_config *cfg = pdev->dev.platform_data;
|
|
const struct platform_device_id *id = pdev->id_entry;
|
|
unsigned int i;
|
|
int ret;
|
|
|
|
if (!cfg) {
|
|
dev_err(&tmu->pdev->dev, "missing platform data\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
tmu->pdev = pdev;
|
|
tmu->model = id->driver_data;
|
|
|
|
/* Get hold of clock. */
|
|
tmu->clk = clk_get(&tmu->pdev->dev,
|
|
tmu->model == SH_TMU_LEGACY ? "tmu_fck" : "fck");
|
|
if (IS_ERR(tmu->clk)) {
|
|
dev_err(&tmu->pdev->dev, "cannot get clock\n");
|
|
return PTR_ERR(tmu->clk);
|
|
}
|
|
|
|
ret = clk_prepare(tmu->clk);
|
|
if (ret < 0)
|
|
goto err_clk_put;
|
|
|
|
/* Map the memory resource. */
|
|
ret = sh_tmu_map_memory(tmu);
|
|
if (ret < 0) {
|
|
dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
|
|
goto err_clk_unprepare;
|
|
}
|
|
|
|
/* Allocate and setup the channels. */
|
|
if (tmu->model == SH_TMU_LEGACY)
|
|
tmu->num_channels = 1;
|
|
else
|
|
tmu->num_channels = hweight8(cfg->channels_mask);
|
|
|
|
tmu->channels = kzalloc(sizeof(*tmu->channels) * tmu->num_channels,
|
|
GFP_KERNEL);
|
|
if (tmu->channels == NULL) {
|
|
ret = -ENOMEM;
|
|
goto err_unmap;
|
|
}
|
|
|
|
if (tmu->model == SH_TMU_LEGACY) {
|
|
ret = sh_tmu_channel_setup(&tmu->channels[0], 0,
|
|
cfg->clockevent_rating != 0,
|
|
cfg->clocksource_rating != 0, tmu);
|
|
if (ret < 0)
|
|
goto err_unmap;
|
|
} else {
|
|
/*
|
|
* Use the first channel as a clock event device and the second
|
|
* channel as a clock source.
|
|
*/
|
|
for (i = 0; i < tmu->num_channels; ++i) {
|
|
ret = sh_tmu_channel_setup(&tmu->channels[i], i,
|
|
i == 0, i == 1, tmu);
|
|
if (ret < 0)
|
|
goto err_unmap;
|
|
}
|
|
}
|
|
|
|
platform_set_drvdata(pdev, tmu);
|
|
|
|
return 0;
|
|
|
|
err_unmap:
|
|
kfree(tmu->channels);
|
|
sh_tmu_unmap_memory(tmu);
|
|
err_clk_unprepare:
|
|
clk_unprepare(tmu->clk);
|
|
err_clk_put:
|
|
clk_put(tmu->clk);
|
|
return ret;
|
|
}
|
|
|
|
static int sh_tmu_probe(struct platform_device *pdev)
|
|
{
|
|
struct sh_tmu_device *tmu = platform_get_drvdata(pdev);
|
|
int ret;
|
|
|
|
if (!is_early_platform_device(pdev)) {
|
|
pm_runtime_set_active(&pdev->dev);
|
|
pm_runtime_enable(&pdev->dev);
|
|
}
|
|
|
|
if (tmu) {
|
|
dev_info(&pdev->dev, "kept as earlytimer\n");
|
|
goto out;
|
|
}
|
|
|
|
tmu = kzalloc(sizeof(*tmu), GFP_KERNEL);
|
|
if (tmu == NULL)
|
|
return -ENOMEM;
|
|
|
|
ret = sh_tmu_setup(tmu, pdev);
|
|
if (ret) {
|
|
kfree(tmu);
|
|
pm_runtime_idle(&pdev->dev);
|
|
return ret;
|
|
}
|
|
if (is_early_platform_device(pdev))
|
|
return 0;
|
|
|
|
out:
|
|
if (tmu->has_clockevent || tmu->has_clocksource)
|
|
pm_runtime_irq_safe(&pdev->dev);
|
|
else
|
|
pm_runtime_idle(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_tmu_remove(struct platform_device *pdev)
|
|
{
|
|
return -EBUSY; /* cannot unregister clockevent and clocksource */
|
|
}
|
|
|
|
static const struct platform_device_id sh_tmu_id_table[] = {
|
|
{ "sh_tmu", SH_TMU_LEGACY },
|
|
{ "sh-tmu", SH_TMU },
|
|
{ "sh-tmu-sh3", SH_TMU_SH3 },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(platform, sh_tmu_id_table);
|
|
|
|
static struct platform_driver sh_tmu_device_driver = {
|
|
.probe = sh_tmu_probe,
|
|
.remove = sh_tmu_remove,
|
|
.driver = {
|
|
.name = "sh_tmu",
|
|
},
|
|
.id_table = sh_tmu_id_table,
|
|
};
|
|
|
|
static int __init sh_tmu_init(void)
|
|
{
|
|
return platform_driver_register(&sh_tmu_device_driver);
|
|
}
|
|
|
|
static void __exit sh_tmu_exit(void)
|
|
{
|
|
platform_driver_unregister(&sh_tmu_device_driver);
|
|
}
|
|
|
|
early_platform_init("earlytimer", &sh_tmu_device_driver);
|
|
subsys_initcall(sh_tmu_init);
|
|
module_exit(sh_tmu_exit);
|
|
|
|
MODULE_AUTHOR("Magnus Damm");
|
|
MODULE_DESCRIPTION("SuperH TMU Timer Driver");
|
|
MODULE_LICENSE("GPL v2");
|