mirror of https://gitee.com/openkylin/linux.git
254 lines
6.7 KiB
C
254 lines
6.7 KiB
C
/*
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* linux/include/asm-arm/arch-cl7500/io.h
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* from linux/include/asm-arm/arch-rpc/io.h
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*
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* Copyright (C) 1997 Russell King
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*
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* Modifications:
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* 06-Dec-1997 RMK Created.
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*/
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#ifndef __ASM_ARM_ARCH_IO_H
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#define __ASM_ARM_ARCH_IO_H
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#define IO_SPACE_LIMIT 0xffffffff
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/*
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* GCC is totally crap at loading/storing data. We try to persuade it
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* to do the right thing by using these whereever possible instead of
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* the above.
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*/
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#define __arch_base_getb(b,o) \
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({ \
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unsigned int v, r = (b); \
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__asm__ __volatile__( \
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"ldrb %0, [%1, %2]" \
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: "=r" (v) \
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: "r" (r), "Ir" (o)); \
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v; \
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})
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#define __arch_base_getl(b,o) \
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({ \
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unsigned int v, r = (b); \
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__asm__ __volatile__( \
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"ldr %0, [%1, %2]" \
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: "=r" (v) \
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: "r" (r), "Ir" (o)); \
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v; \
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})
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#define __arch_base_putb(v,b,o) \
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({ \
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unsigned int r = (b); \
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__asm__ __volatile__( \
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"strb %0, [%1, %2]" \
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: \
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: "r" (v), "r" (r), "Ir" (o)); \
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})
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#define __arch_base_putl(v,b,o) \
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({ \
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unsigned int r = (b); \
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__asm__ __volatile__( \
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"str %0, [%1, %2]" \
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: \
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: "r" (v), "r" (r), "Ir" (o)); \
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})
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/*
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* We use two different types of addressing - PC style addresses, and ARM
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* addresses. PC style accesses the PC hardware with the normal PC IO
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* addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+
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* and are translated to the start of IO. Note that all addresses are
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* shifted left!
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*/
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#define __PORT_PCIO(x) (!((x) & 0x80000000))
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/*
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* Dynamic IO functions - let the compiler
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* optimize the expressions
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*/
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static inline void __outb (unsigned int value, unsigned int port)
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{
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unsigned long temp;
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__asm__ __volatile__(
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"tst %2, #0x80000000\n\t"
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"mov %0, %4\n\t"
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"addeq %0, %0, %3\n\t"
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"strb %1, [%0, %2, lsl #2] @ outb"
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: "=&r" (temp)
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: "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
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: "cc");
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}
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static inline void __outw (unsigned int value, unsigned int port)
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{
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unsigned long temp;
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__asm__ __volatile__(
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"tst %2, #0x80000000\n\t"
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"mov %0, %4\n\t"
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"addeq %0, %0, %3\n\t"
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"str %1, [%0, %2, lsl #2] @ outw"
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: "=&r" (temp)
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: "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
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: "cc");
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}
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static inline void __outl (unsigned int value, unsigned int port)
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{
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unsigned long temp;
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__asm__ __volatile__(
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"tst %2, #0x80000000\n\t"
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"mov %0, %4\n\t"
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"addeq %0, %0, %3\n\t"
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"str %1, [%0, %2, lsl #2] @ outl"
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: "=&r" (temp)
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: "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
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: "cc");
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}
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#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
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static inline unsigned sz __in##fnsuffix (unsigned int port) \
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{ \
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unsigned long temp, value; \
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__asm__ __volatile__( \
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"tst %2, #0x80000000\n\t" \
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"mov %0, %4\n\t" \
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"addeq %0, %0, %3\n\t" \
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"ldr" instr " %1, [%0, %2, lsl #2] @ in" #fnsuffix \
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: "=&r" (temp), "=r" (value) \
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: "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \
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: "cc"); \
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return (unsigned sz)value; \
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}
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static inline unsigned int __ioaddr (unsigned int port) \
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{ \
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if (__PORT_PCIO(port)) \
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return (unsigned int)(PCIO_BASE + (port << 2)); \
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else \
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return (unsigned int)(IO_BASE + (port << 2)); \
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}
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#define DECLARE_IO(sz,fnsuffix,instr) \
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DECLARE_DYN_IN(sz,fnsuffix,instr)
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DECLARE_IO(char,b,"b")
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DECLARE_IO(short,w,"")
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DECLARE_IO(int,l,"")
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#undef DECLARE_IO
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#undef DECLARE_DYN_IN
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/*
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* Constant address IO functions
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*
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* These have to be macros for the 'J' constraint to work -
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* +/-4096 immediate operand.
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*/
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#define __outbc(value,port) \
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({ \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"strb %0, [%1, %2] @ outbc" \
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: : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
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else \
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__asm__ __volatile__( \
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"strb %0, [%1, %2] @ outbc" \
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: : "r" (value), "r" (IO_BASE), "r" ((port) << 2)); \
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})
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#define __inbc(port) \
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({ \
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unsigned char result; \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"ldrb %0, [%1, %2] @ inbc" \
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: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
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else \
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__asm__ __volatile__( \
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"ldrb %0, [%1, %2] @ inbc" \
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: "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
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result; \
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})
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#define __outwc(value,port) \
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({ \
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unsigned long v = value; \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"str %0, [%1, %2] @ outwc" \
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: : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
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else \
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__asm__ __volatile__( \
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"str %0, [%1, %2] @ outwc" \
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: : "r" (v|v<<16), "r" (IO_BASE), "r" ((port) << 2)); \
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})
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#define __inwc(port) \
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({ \
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unsigned short result; \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"ldr %0, [%1, %2] @ inwc" \
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: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
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else \
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__asm__ __volatile__( \
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"ldr %0, [%1, %2] @ inwc" \
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: "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
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result & 0xffff; \
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})
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#define __outlc(value,port) \
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({ \
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unsigned long v = value; \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"str %0, [%1, %2] @ outlc" \
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: : "r" (v), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
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else \
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__asm__ __volatile__( \
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"str %0, [%1, %2] @ outlc" \
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: : "r" (v), "r" (IO_BASE), "r" ((port) << 2)); \
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})
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#define __inlc(port) \
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({ \
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unsigned long result; \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"ldr %0, [%1, %2] @ inlc" \
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: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
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else \
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__asm__ __volatile__( \
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"ldr %0, [%1, %2] @ inlc" \
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: "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
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result; \
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})
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#define __ioaddrc(port) \
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(__PORT_PCIO((port)) ? PCIO_BASE + ((port) << 2) : IO_BASE + ((port) << 2))
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#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
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#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
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#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p))
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#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
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#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
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#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
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#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p))
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/* the following macro is deprecated */
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#define ioaddr(port) __ioaddr((port))
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#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l)
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#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l)
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#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l)
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#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l)
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/*
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* 1:1 mapping for ioremapped regions.
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*/
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#define __mem_pci(x) (x)
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#endif
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