mirror of https://gitee.com/openkylin/linux.git
587 lines
13 KiB
C
587 lines
13 KiB
C
/* QLogic qed NIC Driver
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* Copyright (c) 2015 QLogic Corporation
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*
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* This software is available under the terms of the GNU General Public License
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* (GPL) Version 2, available from the file COPYING in the main directory of
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* this source tree.
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*/
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#ifndef _QED_H
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#define _QED_H
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/firmware.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/workqueue.h>
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#include <linux/zlib.h>
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#include <linux/hashtable.h>
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#include <linux/qed/qed_if.h>
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#include "qed_hsi.h"
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extern const struct qed_common_ops qed_common_ops_pass;
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#define DRV_MODULE_VERSION "8.7.1.20"
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#define MAX_HWFNS_PER_DEVICE (4)
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#define NAME_SIZE 16
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#define VER_SIZE 16
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#define QED_WFQ_UNIT 100
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/* cau states */
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enum qed_coalescing_mode {
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QED_COAL_MODE_DISABLE,
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QED_COAL_MODE_ENABLE
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};
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struct qed_eth_cb_ops;
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struct qed_dev_info;
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/* helpers */
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static inline u32 qed_db_addr(u32 cid, u32 DEMS)
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{
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u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
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FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
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return db_addr;
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}
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#define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
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((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
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~((1 << (p_hwfn->cdev->cache_shift)) - 1))
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#define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++)
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#define D_TRINE(val, cond1, cond2, true1, true2, def) \
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(val == (cond1) ? true1 : \
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(val == (cond2) ? true2 : def))
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/* forward */
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struct qed_ptt_pool;
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struct qed_spq;
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struct qed_sb_info;
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struct qed_sb_attn_info;
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struct qed_cxt_mngr;
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struct qed_sb_sp_info;
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struct qed_mcp_info;
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struct qed_rt_data {
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u32 *init_val;
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bool *b_valid;
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};
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enum qed_tunn_mode {
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QED_MODE_L2GENEVE_TUNN,
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QED_MODE_IPGENEVE_TUNN,
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QED_MODE_L2GRE_TUNN,
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QED_MODE_IPGRE_TUNN,
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QED_MODE_VXLAN_TUNN,
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};
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enum qed_tunn_clss {
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QED_TUNN_CLSS_MAC_VLAN,
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QED_TUNN_CLSS_MAC_VNI,
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QED_TUNN_CLSS_INNER_MAC_VLAN,
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QED_TUNN_CLSS_INNER_MAC_VNI,
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MAX_QED_TUNN_CLSS,
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};
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struct qed_tunn_start_params {
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unsigned long tunn_mode;
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u16 vxlan_udp_port;
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u16 geneve_udp_port;
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u8 update_vxlan_udp_port;
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u8 update_geneve_udp_port;
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u8 tunn_clss_vxlan;
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u8 tunn_clss_l2geneve;
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u8 tunn_clss_ipgeneve;
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u8 tunn_clss_l2gre;
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u8 tunn_clss_ipgre;
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};
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struct qed_tunn_update_params {
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unsigned long tunn_mode_update_mask;
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unsigned long tunn_mode;
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u16 vxlan_udp_port;
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u16 geneve_udp_port;
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u8 update_rx_pf_clss;
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u8 update_tx_pf_clss;
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u8 update_vxlan_udp_port;
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u8 update_geneve_udp_port;
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u8 tunn_clss_vxlan;
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u8 tunn_clss_l2geneve;
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u8 tunn_clss_ipgeneve;
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u8 tunn_clss_l2gre;
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u8 tunn_clss_ipgre;
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};
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/* The PCI personality is not quite synonymous to protocol ID:
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* 1. All personalities need CORE connections
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* 2. The Ethernet personality may support also the RoCE protocol
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*/
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enum qed_pci_personality {
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QED_PCI_ETH,
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QED_PCI_DEFAULT /* default in shmem */
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};
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/* All VFs are symmetric, all counters are PF + all VFs */
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struct qed_qm_iids {
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u32 cids;
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u32 vf_cids;
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u32 tids;
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};
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enum QED_RESOURCES {
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QED_SB,
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QED_L2_QUEUE,
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QED_VPORT,
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QED_RSS_ENG,
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QED_PQ,
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QED_RL,
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QED_MAC,
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QED_VLAN,
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QED_ILT,
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QED_MAX_RESC,
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};
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enum QED_FEATURE {
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QED_PF_L2_QUE,
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QED_VF,
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QED_MAX_FEATURES,
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};
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enum QED_PORT_MODE {
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QED_PORT_MODE_DE_2X40G,
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QED_PORT_MODE_DE_2X50G,
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QED_PORT_MODE_DE_1X100G,
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QED_PORT_MODE_DE_4X10G_F,
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QED_PORT_MODE_DE_4X10G_E,
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QED_PORT_MODE_DE_4X20G,
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QED_PORT_MODE_DE_1X40G,
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QED_PORT_MODE_DE_2X25G,
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QED_PORT_MODE_DE_1X25G
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};
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enum qed_dev_cap {
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QED_DEV_CAP_ETH,
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};
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struct qed_hw_info {
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/* PCI personality */
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enum qed_pci_personality personality;
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/* Resource Allocation scheme results */
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u32 resc_start[QED_MAX_RESC];
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u32 resc_num[QED_MAX_RESC];
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u32 feat_num[QED_MAX_FEATURES];
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#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
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#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
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#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
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u8 num_tc;
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u8 offload_tc;
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u8 non_offload_tc;
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u32 concrete_fid;
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u16 opaque_fid;
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u16 ovlan;
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u32 part_num[4];
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unsigned char hw_mac_addr[ETH_ALEN];
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struct qed_igu_info *p_igu_info;
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u32 port_mode;
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u32 hw_mode;
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unsigned long device_capabilities;
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};
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struct qed_hw_cid_data {
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u32 cid;
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bool b_cid_allocated;
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/* Additional identifiers */
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u16 opaque_fid;
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u8 vport_id;
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};
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/* maximun size of read/write commands (HW limit) */
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#define DMAE_MAX_RW_SIZE 0x2000
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struct qed_dmae_info {
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/* Mutex for synchronizing access to functions */
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struct mutex mutex;
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u8 channel;
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dma_addr_t completion_word_phys_addr;
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/* The memory location where the DMAE writes the completion
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* value when an operation is finished on this context.
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*/
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u32 *p_completion_word;
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dma_addr_t intermediate_buffer_phys_addr;
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/* An intermediate buffer for DMAE operations that use virtual
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* addresses - data is DMA'd to/from this buffer and then
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* memcpy'd to/from the virtual address
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*/
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u32 *p_intermediate_buffer;
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dma_addr_t dmae_cmd_phys_addr;
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struct dmae_cmd *p_dmae_cmd;
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};
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struct qed_wfq_data {
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/* when feature is configured for at least 1 vport */
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u32 min_speed;
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bool configured;
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};
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struct qed_qm_info {
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struct init_qm_pq_params *qm_pq_params;
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struct init_qm_vport_params *qm_vport_params;
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struct init_qm_port_params *qm_port_params;
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u16 start_pq;
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u8 start_vport;
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u8 pure_lb_pq;
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u8 offload_pq;
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u8 pure_ack_pq;
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u8 vf_queues_offset;
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u16 num_pqs;
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u16 num_vf_pqs;
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u8 num_vports;
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u8 max_phys_tcs_per_port;
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bool pf_rl_en;
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bool pf_wfq_en;
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bool vport_rl_en;
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bool vport_wfq_en;
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u8 pf_wfq;
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u32 pf_rl;
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struct qed_wfq_data *wfq_data;
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};
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struct storm_stats {
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u32 address;
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u32 len;
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};
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struct qed_storm_stats {
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struct storm_stats mstats;
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struct storm_stats pstats;
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struct storm_stats tstats;
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struct storm_stats ustats;
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};
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struct qed_fw_data {
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struct fw_ver_info *fw_ver_info;
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const u8 *modes_tree_buf;
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union init_op *init_ops;
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const u32 *arr_data;
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u32 init_ops_size;
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};
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struct qed_simd_fp_handler {
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void *token;
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void (*func)(void *);
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};
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struct qed_hwfn {
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struct qed_dev *cdev;
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u8 my_id; /* ID inside the PF */
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#define IS_LEAD_HWFN(edev) (!((edev)->my_id))
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u8 rel_pf_id; /* Relative to engine*/
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u8 abs_pf_id;
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#define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1)
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u8 port_id;
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bool b_active;
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u32 dp_module;
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u8 dp_level;
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char name[NAME_SIZE];
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bool first_on_engine;
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bool hw_init_done;
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u8 num_funcs_on_engine;
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/* BAR access */
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void __iomem *regview;
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void __iomem *doorbells;
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u64 db_phys_addr;
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unsigned long db_size;
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/* PTT pool */
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struct qed_ptt_pool *p_ptt_pool;
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/* HW info */
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struct qed_hw_info hw_info;
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/* rt_array (for init-tool) */
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struct qed_rt_data rt_data;
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/* SPQ */
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struct qed_spq *p_spq;
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/* EQ */
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struct qed_eq *p_eq;
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/* Consolidate Q*/
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struct qed_consq *p_consq;
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/* Slow-Path definitions */
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struct tasklet_struct *sp_dpc;
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bool b_sp_dpc_enabled;
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struct qed_ptt *p_main_ptt;
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struct qed_ptt *p_dpc_ptt;
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struct qed_sb_sp_info *p_sp_sb;
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struct qed_sb_attn_info *p_sb_attn;
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/* Protocol related */
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struct qed_pf_params pf_params;
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/* Array of sb_info of all status blocks */
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struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
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u16 num_sbs;
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struct qed_cxt_mngr *p_cxt_mngr;
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/* Flag indicating whether interrupts are enabled or not*/
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bool b_int_enabled;
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bool b_int_requested;
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/* True if the driver requests for the link */
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bool b_drv_link_init;
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struct qed_vf_iov *vf_iov_info;
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struct qed_pf_iov *pf_iov_info;
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struct qed_mcp_info *mcp_info;
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struct qed_hw_cid_data *p_tx_cids;
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struct qed_hw_cid_data *p_rx_cids;
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struct qed_dmae_info dmae_info;
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/* QM init */
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struct qed_qm_info qm_info;
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struct qed_storm_stats storm_stats;
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/* Buffer for unzipping firmware data */
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void *unzip_buf;
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struct qed_simd_fp_handler simd_proto_handler[64];
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#ifdef CONFIG_QED_SRIOV
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struct workqueue_struct *iov_wq;
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struct delayed_work iov_task;
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unsigned long iov_task_flags;
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#endif
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struct z_stream_s *stream;
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};
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struct pci_params {
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int pm_cap;
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unsigned long mem_start;
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unsigned long mem_end;
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unsigned int irq;
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u8 pf_num;
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};
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struct qed_int_param {
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u32 int_mode;
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u8 num_vectors;
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u8 min_msix_cnt; /* for minimal functionality */
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};
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struct qed_int_params {
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struct qed_int_param in;
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struct qed_int_param out;
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struct msix_entry *msix_table;
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bool fp_initialized;
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u8 fp_msix_base;
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u8 fp_msix_cnt;
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};
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struct qed_dev {
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u32 dp_module;
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u8 dp_level;
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char name[NAME_SIZE];
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u8 type;
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#define QED_DEV_TYPE_BB (0 << 0)
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#define QED_DEV_TYPE_AH BIT(0)
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/* Translate type/revision combo into the proper conditions */
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#define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
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#define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \
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CHIP_REV_IS_A0(dev))
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#define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \
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CHIP_REV_IS_B0(dev))
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#define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
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QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
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u16 vendor_id;
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u16 device_id;
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u16 chip_num;
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#define CHIP_NUM_MASK 0xffff
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#define CHIP_NUM_SHIFT 16
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u16 chip_rev;
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#define CHIP_REV_MASK 0xf
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#define CHIP_REV_SHIFT 12
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#define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev)
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#define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)
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u16 chip_metal;
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#define CHIP_METAL_MASK 0xff
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#define CHIP_METAL_SHIFT 4
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u16 chip_bond_id;
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#define CHIP_BOND_ID_MASK 0xf
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#define CHIP_BOND_ID_SHIFT 0
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u8 num_engines;
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u8 num_ports_in_engines;
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u8 num_funcs_in_port;
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u8 path_id;
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enum qed_mf_mode mf_mode;
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#define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
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#define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
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#define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)
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int pcie_width;
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int pcie_speed;
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u8 ver_str[VER_SIZE];
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/* Add MF related configuration */
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u8 mcp_rev;
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u8 boot_mode;
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u8 wol;
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u32 int_mode;
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enum qed_coalescing_mode int_coalescing_mode;
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u8 rx_coalesce_usecs;
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u8 tx_coalesce_usecs;
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/* Start Bar offset of first hwfn */
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void __iomem *regview;
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void __iomem *doorbells;
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u64 db_phys_addr;
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unsigned long db_size;
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/* PCI */
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u8 cache_shift;
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/* Init */
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const struct iro *iro_arr;
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#define IRO (p_hwfn->cdev->iro_arr)
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/* HW functions */
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u8 num_hwfns;
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struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
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/* SRIOV */
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struct qed_hw_sriov_info *p_iov_info;
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#define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info)
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unsigned long tunn_mode;
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bool b_is_vf;
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u32 drv_type;
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struct qed_eth_stats *reset_stats;
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struct qed_fw_data *fw_data;
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u32 mcp_nvm_resp;
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/* Linux specific here */
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struct qede_dev *edev;
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struct pci_dev *pdev;
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int msg_enable;
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struct pci_params pci_params;
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struct qed_int_params int_params;
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u8 protocol;
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#define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH)
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/* Callbacks to protocol driver */
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union {
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struct qed_common_cb_ops *common;
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struct qed_eth_cb_ops *eth;
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} protocol_ops;
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void *ops_cookie;
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|
|
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const struct firmware *firmware;
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|
};
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|
|
|
#define NUM_OF_VFS(dev) MAX_NUM_VFS_BB
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|
#define NUM_OF_L2_QUEUES(dev) MAX_NUM_L2_QUEUES_BB
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|
#define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB
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|
#define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB
|
|
|
|
/**
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|
* @brief qed_concrete_to_sw_fid - get the sw function id from
|
|
* the concrete value.
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|
*
|
|
* @param concrete_fid
|
|
*
|
|
* @return inline u8
|
|
*/
|
|
static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
|
|
u32 concrete_fid)
|
|
{
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|
u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
|
|
|
|
return pfid;
|
|
}
|
|
|
|
#define PURE_LB_TC 8
|
|
|
|
void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate);
|
|
|
|
#define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
|
|
|
|
/* Other Linux specific common definitions */
|
|
#define DP_NAME(cdev) ((cdev)->name)
|
|
|
|
#define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\
|
|
(cdev->regview) + \
|
|
(offset))
|
|
|
|
#define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
|
|
#define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
|
|
#define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
|
|
|
|
#define DOORBELL(cdev, db_addr, val) \
|
|
writel((u32)val, (void __iomem *)((u8 __iomem *)\
|
|
(cdev->doorbells) + (db_addr)))
|
|
|
|
/* Prototypes */
|
|
int qed_fill_dev_info(struct qed_dev *cdev,
|
|
struct qed_dev_info *dev_info);
|
|
void qed_link_update(struct qed_hwfn *hwfn);
|
|
u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
|
|
u32 input_len, u8 *input_buf,
|
|
u32 max_size, u8 *unzip_buf);
|
|
|
|
int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
|
|
|
|
#endif /* _QED_H */
|