190 lines
8.1 KiB
Diff
190 lines
8.1 KiB
Diff
From 616289ed29225c0ddfe5699c7fdf42a0fcbe0ab4 Mon Sep 17 00:00:00 2001
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From: Jessica Clarke <jrtc27@jrtc27.com>
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Date: Wed, 1 Apr 2020 15:50:47 +0100
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Subject: [PATCH] [LegalizeTypes][RISCV] Correctly sign-extend comparison for
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ATOMIC_CMP_XCHG
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Summary:
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Currently, the comparison argument used for ATOMIC_CMP_XCHG is legalised
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with GetPromotedInteger, which leaves the upper bits of the value
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undefind. Since this is used for comparing in an LR/SC loop with a
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full-width comparison, we must sign extend it. We introduce a new
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getExtendForAtomicCmpSwapArg to complement getExtendForAtomicOps, since
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many targets have compare-and-swap instructions (or pseudos) that
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correctly handle an any-extend input, and the existing function
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determines the extension of the result, whereas we are concerned with
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the input.
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This is related to https://reviews.llvm.org/D58829, which solved the
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issue for ATOMIC_CMP_SWAP_WITH_SUCCESS, but not the simpler
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ATOMIC_CMP_SWAP.
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Reviewers: asb, lenary, efriedma
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Reviewed By: asb
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Subscribers: arichardson, hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, jfb, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, evandro, llvm-commits
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Tags: #llvm
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Differential Revision: https://reviews.llvm.org/D74453
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---
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llvm/include/llvm/CodeGen/TargetLowering.h | 12 ++++++++++++
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.../SelectionDAG/LegalizeIntegerTypes.cpp | 18 +++++++++++++++++-
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llvm/lib/Target/RISCV/RISCVISelLowering.h | 4 ++++
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llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll | 10 ++++++++++
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4 files changed, 43 insertions(+), 1 deletion(-)
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diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
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index fefa8daa60a1..99601c436651 100644
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--- a/llvm/include/llvm/CodeGen/TargetLowering.h
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+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
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@@ -1962,6 +1962,18 @@ class TargetLoweringBase {
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return ISD::ZERO_EXTEND;
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}
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+ /// Returns how the platform's atomic compare and swap expects its comparison
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+ /// value to be extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND). This is
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+ /// separate from getExtendForAtomicOps, which is concerned with the
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+ /// sign-extension of the instruction's output, whereas here we are concerned
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+ /// with the sign-extension of the input. For targets with compare-and-swap
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+ /// instructions (or sub-word comparisons in their LL/SC loop expansions),
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+ /// the input can be ANY_EXTEND, but the output will still have a specific
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+ /// extension.
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+ virtual ISD::NodeType getExtendForAtomicCmpSwapArg() const {
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+ return ISD::ANY_EXTEND;
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+ }
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+
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/// @}
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/// Returns true if we should normalize
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diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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index 0248b5121e3f..ed67f7dc8ea3 100644
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--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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@@ -278,8 +278,24 @@ SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
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return Res.getValue(1);
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}
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- SDValue Op2 = GetPromotedInteger(N->getOperand(2));
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+ // Op2 is used for the comparison and thus must be extended according to the
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+ // target's atomic operations. Op3 is merely stored and so can be left alone.
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+ SDValue Op2 = N->getOperand(2);
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SDValue Op3 = GetPromotedInteger(N->getOperand(3));
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+ switch (TLI.getExtendForAtomicCmpSwapArg()) {
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+ case ISD::SIGN_EXTEND:
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+ Op2 = SExtPromotedInteger(Op2);
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+ break;
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+ case ISD::ZERO_EXTEND:
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+ Op2 = ZExtPromotedInteger(Op2);
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+ break;
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+ case ISD::ANY_EXTEND:
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+ Op2 = GetPromotedInteger(Op2);
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+ break;
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+ default:
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+ llvm_unreachable("Invalid atomic op extension");
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+ }
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+
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SDVTList VTs =
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DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
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SDValue Res = DAG.getAtomicCmpSwap(
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diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
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index 929169dd62d9..f76abf22e4db 100644
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--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
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+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
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@@ -129,6 +129,10 @@ class RISCVTargetLowering : public TargetLowering {
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return ISD::SIGN_EXTEND;
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}
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+ ISD::NodeType getExtendForAtomicCmpSwapArg() const override {
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+ return ISD::SIGN_EXTEND;
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+ }
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+
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bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
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if (DAG.getMachineFunction().getFunction().hasMinSize())
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return false;
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diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
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index 43da05ebe7c7..f2691ba1a771 100644
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--- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
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+++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
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@@ -1628,6 +1628,7 @@ define void @cmpxchg_i32_monotonic_monotonic(i32* %ptr, i32 %cmp, i32 %val) noun
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;
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; RV64IA-LABEL: cmpxchg_i32_monotonic_monotonic:
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; RV64IA: # %bb.0:
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+; RV64IA-NEXT: sext.w a1, a1
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; RV64IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
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; RV64IA-NEXT: lr.w a3, (a0)
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; RV64IA-NEXT: bne a3, a1, .LBB20_3
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@@ -1680,6 +1681,7 @@ define void @cmpxchg_i32_acquire_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi
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;
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; RV64IA-LABEL: cmpxchg_i32_acquire_monotonic:
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; RV64IA: # %bb.0:
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+; RV64IA-NEXT: sext.w a1, a1
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; RV64IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
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; RV64IA-NEXT: lr.w.aq a3, (a0)
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; RV64IA-NEXT: bne a3, a1, .LBB21_3
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@@ -1732,6 +1734,7 @@ define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind
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;
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; RV64IA-LABEL: cmpxchg_i32_acquire_acquire:
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; RV64IA: # %bb.0:
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+; RV64IA-NEXT: sext.w a1, a1
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; RV64IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
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; RV64IA-NEXT: lr.w.aq a3, (a0)
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; RV64IA-NEXT: bne a3, a1, .LBB22_3
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@@ -1784,6 +1787,7 @@ define void @cmpxchg_i32_release_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi
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;
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; RV64IA-LABEL: cmpxchg_i32_release_monotonic:
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; RV64IA: # %bb.0:
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+; RV64IA-NEXT: sext.w a1, a1
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; RV64IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
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; RV64IA-NEXT: lr.w a3, (a0)
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; RV64IA-NEXT: bne a3, a1, .LBB23_3
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@@ -1836,6 +1840,7 @@ define void @cmpxchg_i32_release_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind
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;
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; RV64IA-LABEL: cmpxchg_i32_release_acquire:
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; RV64IA: # %bb.0:
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+; RV64IA-NEXT: sext.w a1, a1
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; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
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; RV64IA-NEXT: lr.w a3, (a0)
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; RV64IA-NEXT: bne a3, a1, .LBB24_3
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@@ -1888,6 +1893,7 @@ define void @cmpxchg_i32_acq_rel_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi
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;
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; RV64IA-LABEL: cmpxchg_i32_acq_rel_monotonic:
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; RV64IA: # %bb.0:
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+; RV64IA-NEXT: sext.w a1, a1
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; RV64IA-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1
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; RV64IA-NEXT: lr.w.aq a3, (a0)
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; RV64IA-NEXT: bne a3, a1, .LBB25_3
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@@ -1940,6 +1946,7 @@ define void @cmpxchg_i32_acq_rel_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind
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;
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; RV64IA-LABEL: cmpxchg_i32_acq_rel_acquire:
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; RV64IA: # %bb.0:
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+; RV64IA-NEXT: sext.w a1, a1
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; RV64IA-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1
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; RV64IA-NEXT: lr.w.aq a3, (a0)
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; RV64IA-NEXT: bne a3, a1, .LBB26_3
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@@ -1992,6 +1999,7 @@ define void @cmpxchg_i32_seq_cst_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi
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;
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; RV64IA-LABEL: cmpxchg_i32_seq_cst_monotonic:
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; RV64IA: # %bb.0:
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+; RV64IA-NEXT: sext.w a1, a1
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; RV64IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
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; RV64IA-NEXT: lr.w.aqrl a3, (a0)
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; RV64IA-NEXT: bne a3, a1, .LBB27_3
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@@ -2044,6 +2052,7 @@ define void @cmpxchg_i32_seq_cst_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind
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;
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; RV64IA-LABEL: cmpxchg_i32_seq_cst_acquire:
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; RV64IA: # %bb.0:
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+; RV64IA-NEXT: sext.w a1, a1
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; RV64IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
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; RV64IA-NEXT: lr.w.aqrl a3, (a0)
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; RV64IA-NEXT: bne a3, a1, .LBB28_3
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@@ -2096,6 +2105,7 @@ define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) nounwind
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;
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; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
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; RV64IA: # %bb.0:
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+; RV64IA-NEXT: sext.w a1, a1
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; RV64IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
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; RV64IA-NEXT: lr.w.aqrl a3, (a0)
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; RV64IA-NEXT: bne a3, a1, .LBB29_3
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