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ARM: DRA7: hwmod: Fixup SATA hwmod 

Get rid of optional clock as that is now managed by the
AHCI platform driver.

Correct .mpu_rt_idx to 1 as the module register space (SYSCONFIG..)
is passed as the second memory resource in the device tree.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Rajendra Nayak <rnayak@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
Roger Quadros 2014-07-06 15:51:24 -06:00 committed by Paul Walmsley
parent 0cd8d4052a
commit 1ea0999e08
1 changed files with 1 additions and 5 deletions
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6
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
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@ -1268,9 +1268,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
}; };
/* sata */ /* sata */
static struct omap_hwmod_opt_clk sata_opt_clks[] = {
{ .role = "ref_clk", .clk = "sata_ref_clk" },
};
static struct omap_hwmod dra7xx_sata_hwmod = { static struct omap_hwmod dra7xx_sata_hwmod = {
.name = "sata", .name = "sata",
@ -1278,6 +1275,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
.clkdm_name = "l3init_clkdm", .clkdm_name = "l3init_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "func_48m_fclk", .main_clk = "func_48m_fclk",
.mpu_rt_idx = 1,
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET, .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
@ -1285,8 +1283,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
.modulemode = MODULEMODE_SWCTRL, .modulemode = MODULEMODE_SWCTRL,
}, },
}, },
.opt_clks = sata_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
}; };
/* /*