coresight: remove the unnecessary configuration coresight-default-sink
The coresight-default-sink configuration option has been removed from the framework. As such remove it from DT and bindings. Signed-off-by: Kaixu Xia <xiakaixu@huawei.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -61,7 +61,6 @@ Example:
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0 0x20010000 0 0x1000>;
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coresight-default-sink;
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clocks = <&oscclk6a>;
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clock-names = "apb_pclk";
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port {
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@ -275,7 +275,6 @@ etb@0,e3c42000 {
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0 0xe3c42000 0 0x1000>;
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coresight-default-sink;
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clocks = <&clk_375m>;
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clock-names = "apb_pclk";
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port {
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@ -150,7 +150,6 @@ etb@5401b000 {
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0x5401b000 0x1000>;
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coresight-default-sink;
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clocks = <&emu_src_ck>;
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clock-names = "apb_pclk";
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port {
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@ -145,7 +145,6 @@ etb@540000000 {
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0x5401b000 0x1000>;
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coresight-default-sink;
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clocks = <&emu_src_ck>;
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clock-names = "apb_pclk";
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port {
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@ -362,7 +362,6 @@ etb@0,20010000 {
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0 0x20010000 0 0x1000>;
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coresight-default-sink;
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clocks = <&oscclk6a>;
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clock-names = "apb_pclk";
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port {
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