iommu/arm-smmu: use relaxed accessors where possible
Apart from fault handling and page table manipulation, we don't care about memory ordering between SMMU control registers and normal, cacheable memory, so use the _relaxed I/O accessors wherever possible. Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -778,7 +778,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
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#ifdef __BIG_ENDIAN
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#ifdef __BIG_ENDIAN
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reg |= SCTLR_E;
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reg |= SCTLR_E;
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#endif
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#endif
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writel(reg, cb_base + ARM_SMMU_CB_SCTLR);
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writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
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}
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}
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static int arm_smmu_init_domain_context(struct iommu_domain *domain,
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static int arm_smmu_init_domain_context(struct iommu_domain *domain,
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@ -1595,7 +1595,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
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/* Push the button */
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/* Push the button */
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arm_smmu_tlb_sync(smmu);
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arm_smmu_tlb_sync(smmu);
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writel(scr0, gr0_base + ARM_SMMU_GR0_sCR0);
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writel_relaxed(scr0, gr0_base + ARM_SMMU_GR0_sCR0);
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}
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}
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static int arm_smmu_id_size_to_bits(int size)
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static int arm_smmu_id_size_to_bits(int size)
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@ -1928,7 +1928,7 @@ static int arm_smmu_device_remove(struct platform_device *pdev)
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free_irq(smmu->irqs[i], smmu);
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free_irq(smmu->irqs[i], smmu);
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/* Turn the thing off */
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/* Turn the thing off */
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writel(sCR0_CLIENTPD, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_sCR0);
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writel_relaxed(sCR0_CLIENTPD, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_sCR0);
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return 0;
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return 0;
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}
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}
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