fbdev: sh_mipi_dsi: add lane control support
SH MIPI DSI can use 0-4 lane Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
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@ -324,6 +324,7 @@ static struct resource mipidsi0_resources[] = {
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static struct sh_mipi_dsi_info mipidsi0_info = {
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static struct sh_mipi_dsi_info mipidsi0_info = {
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.data_format = MIPI_RGB888,
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.data_format = MIPI_RGB888,
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.lcd_chan = &lcdc0_info.ch[0],
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.lcd_chan = &lcdc0_info.ch[0],
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.lane = 2,
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.vsynw_offset = 20,
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.vsynw_offset = 20,
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.clksrc = 1,
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.clksrc = 1,
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.flags = SH_MIPI_DSI_HSABM,
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.flags = SH_MIPI_DSI_HSABM,
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@ -580,6 +580,7 @@ static struct resource mipidsi0_resources[] = {
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static struct sh_mipi_dsi_info mipidsi0_info = {
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static struct sh_mipi_dsi_info mipidsi0_info = {
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.data_format = MIPI_RGB888,
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.data_format = MIPI_RGB888,
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.lcd_chan = &lcdc_info.ch[0],
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.lcd_chan = &lcdc_info.ch[0],
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.lane = 2,
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.vsynw_offset = 17,
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.vsynw_offset = 17,
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};
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};
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@ -8,6 +8,7 @@
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* published by the Free Software Foundation.
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* published by the Free Software Foundation.
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*/
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*/
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#include <linux/bitmap.h>
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#include <linux/clk.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/init.h>
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@ -153,6 +154,7 @@ static int __init sh_mipi_setup(struct sh_mipi *mipi,
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struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
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struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
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u32 pctype, datatype, pixfmt, linelength, vmctr2 = 0x00e00000;
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u32 pctype, datatype, pixfmt, linelength, vmctr2 = 0x00e00000;
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bool yuv;
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bool yuv;
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u32 tmp;
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/*
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/*
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* Select data format. MIPI DSI is not hot-pluggable, so, we just use
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* Select data format. MIPI DSI is not hot-pluggable, so, we just use
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@ -253,6 +255,9 @@ static int __init sh_mipi_setup(struct sh_mipi *mipi,
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(!yuv && ch->interface_type != RGB24))
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(!yuv && ch->interface_type != RGB24))
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return -EINVAL;
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return -EINVAL;
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if (!pdata->lane)
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return -EINVAL;
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/* reset DSI link */
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/* reset DSI link */
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iowrite32(0x00000001, base + SYSCTRL);
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iowrite32(0x00000001, base + SYSCTRL);
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/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
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/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
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@ -269,7 +274,10 @@ static int __init sh_mipi_setup(struct sh_mipi *mipi,
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* ECC check enable
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* ECC check enable
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* additionally enable first two lanes
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* additionally enable first two lanes
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*/
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*/
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iowrite32(0x00003703, base + SYSCONF);
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bitmap_fill((unsigned long *)&tmp, pdata->lane);
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tmp |= 0x00003700;
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iowrite32(tmp, base + SYSCONF);
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/*
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/*
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* T_wakeup = 0x7000
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* T_wakeup = 0x7000
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* T_hs-trail = 3
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* T_hs-trail = 3
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@ -35,6 +35,7 @@ struct sh_mobile_lcdc_chan_cfg;
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struct sh_mipi_dsi_info {
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struct sh_mipi_dsi_info {
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enum sh_mipi_dsi_data_fmt data_format;
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enum sh_mipi_dsi_data_fmt data_format;
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struct sh_mobile_lcdc_chan_cfg *lcd_chan;
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struct sh_mobile_lcdc_chan_cfg *lcd_chan;
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int lane;
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unsigned long flags;
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unsigned long flags;
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u32 clksrc;
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u32 clksrc;
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unsigned int vsynw_offset;
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unsigned int vsynw_offset;
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