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ARM: AT91: pm: Factorize standby function 

Detect presence of second bank. So we do not need to have on function per SoC

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD 2013-10-16 16:24:56 +02:00 committed by Daniel Lezcano
parent 1ce3c48e6c
commit 2d2c476f3c
6 changed files with 29 additions and 36 deletions
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2
arch/arm/mach-at91/at91sam9260.c
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@ -353,7 +353,7 @@ static void __init at91sam9260_initialize(void)
/* Register GPIO subsystem */ /* Register GPIO subsystem */
at91_gpio_init(at91sam9260_gpio, 3); at91_gpio_init(at91sam9260_gpio, 3);
at91_pm_set_standby(at91sam9_standby); at91_pm_set_standby(at91sam9_sdram_standby);
} }
/* -------------------------------------------------------------------- /* --------------------------------------------------------------------

2
arch/arm/mach-at91/at91sam9261.c
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@ -295,7 +295,7 @@ static void __init at91sam9261_initialize(void)
/* Register GPIO subsystem */ /* Register GPIO subsystem */
at91_gpio_init(at91sam9261_gpio, 3); at91_gpio_init(at91sam9261_gpio, 3);
at91_pm_set_sandby(at91sam9_standby); at91_pm_set_standby(at91sam9_sdram_standby);
} }
/* -------------------------------------------------------------------- /* --------------------------------------------------------------------

2
arch/arm/mach-at91/at91sam9263.c
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@ -332,7 +332,7 @@ static void __init at91sam9263_initialize(void)
/* Register GPIO subsystem */ /* Register GPIO subsystem */
at91_gpio_init(at91sam9263_gpio, 5); at91_gpio_init(at91sam9263_gpio, 5);
at91_pm_set_standby(at91sam9263_standby); at91_pm_set_standby(at91sam9_sdram_standby);
} }
/* -------------------------------------------------------------------- /* --------------------------------------------------------------------

2
arch/arm/mach-at91/at91sam9g45.c
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@ -381,7 +381,7 @@ static void __init at91sam9g45_initialize(void)
/* Register GPIO subsystem */ /* Register GPIO subsystem */
at91_gpio_init(at91sam9g45_gpio, 5); at91_gpio_init(at91sam9g45_gpio, 5);
at91_pm_set_standby(at91sam9g45_standby); at91_pm_set_standby(at91_ddr_standby);
} }
/* -------------------------------------------------------------------- /* --------------------------------------------------------------------

2
arch/arm/mach-at91/at91sam9rl.c
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@ -298,7 +298,7 @@ static void __init at91sam9rl_initialize(void)
/* Register GPIO subsystem */ /* Register GPIO subsystem */
at91_gpio_init(at91sam9rl_gpio, 4); at91_gpio_init(at91sam9rl_gpio, 4);
at91_pm_set_standby(at91sam9_standby); at91_pm_set_standby(at91sam9_sdram_standby);
} }
/* -------------------------------------------------------------------- /* --------------------------------------------------------------------

55
arch/arm/mach-at91/pm.h
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@ -49,16 +49,18 @@ static inline void at91rm9200_standby(void)
/* We manage both DDRAM/SDRAM controllers, we need more than one value to /* We manage both DDRAM/SDRAM controllers, we need more than one value to
* remember. * remember.
*/ */
static inline void at91sam9g45_standby(void) static inline void at91_ddr_standby(void)
{ {
/* Those two values allow us to delay self-refresh activation /* Those two values allow us to delay self-refresh activation
* to the maximum. */ * to the maximum. */
u32 lpr0, lpr1; u32 lpr0, lpr1 = 0;
u32 saved_lpr0, saved_lpr1; u32 saved_lpr0, saved_lpr1 = 0;
saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); if (at91_ramc_base[1]) {
lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
}
saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
@ -66,25 +68,29 @@ static inline void at91sam9g45_standby(void)
/* self-refresh mode now */ /* self-refresh mode now */
at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); if (at91_ramc_base[1])
at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
cpu_do_idle(); cpu_do_idle();
at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); if (at91_ramc_base[1])
at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
} }
/* We manage both DDRAM/SDRAM controllers, we need more than one value to /* We manage both DDRAM/SDRAM controllers, we need more than one value to
* remember. * remember.
*/ */
static inline void at91sam9263_standby(void) static inline void at91sam9_sdram_standby(void)
{ {
u32 lpr0, lpr1; u32 lpr0, lpr1 = 0;
u32 saved_lpr0, saved_lpr1; u32 saved_lpr0, saved_lpr1 = 0;
saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); if (at91_ramc_base[1]) {
lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
}
saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
@ -92,27 +98,14 @@ static inline void at91sam9263_standby(void)
/* self-refresh mode now */ /* self-refresh mode now */
at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); if (at91_ramc_base[1])
at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
cpu_do_idle(); cpu_do_idle();
at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); if (at91_ramc_base[1])
} at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
static inline void at91sam9_standby(void)
{
u32 saved_lpr, lpr;
saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
at91_ramc_write(0, AT91_SDRAMC_LPR, lpr |
AT91_SDRAMC_LPCB_SELF_REFRESH);
cpu_do_idle();
at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr);
} }
#endif #endif