drm/i915: Rename variables to be consistent with bspec
Since the code seems insistent on using the variable names from the bspec formulat, let's be consistent and use those names for all the things. For some reason 'link_clk' and 'lanes' were left out in the code until now. Cc: Anshuman Gupta <anshuman.gupta@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200429185457.26235-2-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
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@ -526,6 +526,7 @@ static unsigned int get_hblank_early_enable_config(struct intel_encoder *encoder
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unsigned int hblank_rise, hblank_early_prog;
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unsigned int h_active, h_total, hblank_delta, pixel_clk;
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unsigned int fec_coeff, cdclk, vdsc_bpp;
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unsigned int link_clk, lanes;
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h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
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h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
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@ -534,40 +535,40 @@ static unsigned int get_hblank_early_enable_config(struct intel_encoder *encoder
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cdclk = i915->cdclk.hw.cdclk;
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/* fec= 0.972261, using rounding multiplier of 1000000 */
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fec_coeff = 972261;
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link_clk = crtc_state->port_clock;
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lanes = crtc_state->lane_count;
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drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
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"lanes = %u vdsc_bpp = %u cdclk = %u\n",
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h_active, crtc_state->port_clock, crtc_state->lane_count,
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vdsc_bpp, cdclk);
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h_active, link_clk, lanes, vdsc_bpp, cdclk);
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if (WARN_ON(!crtc_state->port_clock || !crtc_state->lane_count ||
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!crtc_state->dsc.compressed_bpp || !i915->cdclk.hw.cdclk))
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if (WARN_ON(!link_clk || !lanes || !vdsc_bpp || !cdclk))
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return 0;
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link_clks_available = ((((h_total - h_active) *
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((crtc_state->port_clock * ROUNDING_FACTOR) /
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((link_clk * ROUNDING_FACTOR) /
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pixel_clk)) / ROUNDING_FACTOR) - 28);
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link_clks_required = DIV_ROUND_UP(192000, (1000 * pixel_clk / h_total)) * ((48 /
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crtc_state->lane_count) + 2);
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lanes) + 2);
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if (link_clks_available > link_clks_required)
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hblank_delta = 32;
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else
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hblank_delta = DIV_ROUND_UP(((((5 * ROUNDING_FACTOR) /
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crtc_state->port_clock) + ((5 *
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link_clk) + ((5 *
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ROUNDING_FACTOR) /
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cdclk)) * pixel_clk),
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ROUNDING_FACTOR);
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tu_data = (pixel_clk * vdsc_bpp * 8) / ((crtc_state->port_clock *
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crtc_state->lane_count * fec_coeff) / 1000000);
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tu_line = (((h_active * crtc_state->port_clock * fec_coeff) /
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tu_data = (pixel_clk * vdsc_bpp * 8) / ((link_clk *
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lanes * fec_coeff) / 1000000);
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tu_line = (((h_active * link_clk * fec_coeff) /
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1000000) / (64 * pixel_clk));
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link_clks_active = (tu_line - 1) * 64 + tu_data;
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hblank_rise = ((link_clks_active + 6 * DIV_ROUND_UP(link_clks_active,
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250) + 4) * ((pixel_clk * ROUNDING_FACTOR) /
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crtc_state->port_clock)) / ROUNDING_FACTOR;
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link_clk)) / ROUNDING_FACTOR;
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hblank_early_prog = h_active - hblank_rise + hblank_delta;
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@ -577,16 +578,19 @@ static unsigned int get_hblank_early_enable_config(struct intel_encoder *encoder
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static unsigned int get_sample_room_req_config(const struct intel_crtc_state *crtc_state)
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{
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unsigned int h_active, h_total, pixel_clk;
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unsigned int link_clk, lanes;
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unsigned int samples_room;
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h_active = crtc_state->hw.adjusted_mode.hdisplay;
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h_total = crtc_state->hw.adjusted_mode.htotal;
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pixel_clk = crtc_state->hw.adjusted_mode.clock;
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link_clk = crtc_state->port_clock;
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lanes = crtc_state->lane_count;
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samples_room = ((((h_total - h_active) * ((crtc_state->port_clock *
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samples_room = ((((h_total - h_active) * ((link_clk *
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ROUNDING_FACTOR) / pixel_clk)) /
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ROUNDING_FACTOR) - 12) / ((48 /
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crtc_state->lane_count) + 2);
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lanes) + 2);
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return samples_room;
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}
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