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FROMLIST: iommu/mediatek: Allow page table PA up to 35bit 

Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA. So add
the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT to let level 1 and level 2
pgtable support at most 35bit PA.

Signed-off-by: Ning Li <ning.li@mediatek.com>
Link: https://lore.kernel.org/linux-mediatek/20220616120713.12728-3-yf.wang@mediatek.com/
Bug: 235767992
Signed-off-by: Yunfei Wang <yf.wang@mediatek.com>
Change-Id: Iaf93281e99985403d92157aee13e2e449b876545
This commit is contained in:
Yunfei Wang 2022-06-16 20:34:45 +08:00 committed by Suren Baghdasaryan
parent 0b6600b792
commit 4ee2f8b56d
1 changed files with 13 additions and 4 deletions
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17
drivers/iommu/mtk_iommu.c
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@ -118,6 +118,7 @@
#define WR_THROT_EN BIT(6)
#define HAS_LEGACY_IVRP_PADDR BIT(7)
#define IOVA_34_EN BIT(8)
#define PGTABLE_PA_35_EN BIT(9)
#define MTK_IOMMU_HAS_FLAG(pdata, _x) \
((((pdata)->flags) & (_x)) == (_x))
@ -125,6 +126,7 @@
struct mtk_iommu_domain {
struct io_pgtable_cfg cfg;
struct io_pgtable_ops *iop;
u32 ttbr;
struct mtk_iommu_data *data;
struct iommu_domain domain;
@ -393,6 +395,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
if (data->m4u_dom) {
dom->iop = data->m4u_dom->iop;
dom->cfg = data->m4u_dom->cfg;
dom->ttbr = data->m4u_dom->ttbr;
dom->domain.pgsize_bitmap = data->m4u_dom->cfg.pgsize_bitmap;
goto update_iova_region;
}
@ -406,6 +409,9 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
.iommu_dev = data->dev,
};
if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT;
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
dom->cfg.oas = data->enable_4GB ? 33 : 32;
else
@ -416,6 +422,9 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
dev_err(data->dev, "Failed to alloc io pgtable\n");
return -EINVAL;
}
dom->ttbr = dom->cfg.quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
dom->cfg.arm_v7s_cfg.ttbr :
dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK;
/* Update our support page sizes bitmap */
dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap;
@ -477,8 +486,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
return ret;
}
data->m4u_dom = dom;
writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
data->base + REG_MMU_PT_BASE_ADDR);
writel(data->m4u_dom->ttbr, data->base + REG_MMU_PT_BASE_ADDR);
pm_runtime_put(m4udev);
}
@ -1009,7 +1017,7 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR);
writel(m4u_dom->ttbr, base + REG_MMU_PT_BASE_ADDR);
return 0;
}
@ -1030,7 +1038,8 @@ static const struct mtk_iommu_plat_data mt2712_data = {
static const struct mtk_iommu_plat_data mt6779_data = {
.m4u_plat = M4U_MT6779,
.flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN,
.flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN |
PGTABLE_PA_35_EN,
.inv_sel_reg = REG_MMU_INV_SEL_GEN2,
.iova_region = single_domain,
.iova_region_nr = ARRAY_SIZE(single_domain),