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drm/i915: crc support for hsw 

hw designers decided to change the CRC registers and coalesce them all
into one. Otherwise nothing changed. I've opted for a new hsw_ version
to grab the crc sample since hsw+1 will have the same crc registers,
but different interrupt source registers. So this little helper
function will come handy there.

Also refactor the display error handler with a neat pipe loop.

v2: Use for_each_pipe.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2013-10-16 22:55:52 +02:00
parent e309a99770
commit 5a69b89f85
3 changed files with 27 additions and 20 deletions
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2
drivers/gpu/drm/i915/i915_debugfs.c
View File

@ -1997,7 +1997,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
u32 val; u32 val;
int ret; int ret;
if (!(IS_IVYBRIDGE(dev) || IS_GEN5(dev) || IS_GEN6(dev))) if (!(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)))
return -ENODEV; return -ENODEV;
if (pipe_crc->source == source) if (pipe_crc->source == source)

44
drivers/gpu/drm/i915/i915_irq.c
View File

@ -1228,6 +1228,15 @@ static void display_pipe_crc_update(struct drm_device *dev, enum pipe pipe,
wake_up_interruptible(&pipe_crc->wq); wake_up_interruptible(&pipe_crc->wq);
} }
static void hsw_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
display_pipe_crc_update(dev, pipe,
I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
0, 0, 0, 0);
}
static void ivb_pipe_crc_update(struct drm_device *dev, enum pipe pipe) static void ivb_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
@ -1252,6 +1261,7 @@ static void ilk_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
I915_READ(PIPE_CRC_RES_RES2_ILK(pipe))); I915_READ(PIPE_CRC_RES_RES2_ILK(pipe)));
} }
#else #else
static inline void hsw_pipe_crc_update(struct drm_device *dev, int pipe) {}
static inline void ivb_pipe_crc_update(struct drm_device *dev, int pipe) {} static inline void ivb_pipe_crc_update(struct drm_device *dev, int pipe) {}
static inline void ilk_pipe_crc_update(struct drm_device *dev, int pipe) {} static inline void ilk_pipe_crc_update(struct drm_device *dev, int pipe) {}
#endif #endif
@ -1418,30 +1428,26 @@ static void ivb_err_int_handler(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
u32 err_int = I915_READ(GEN7_ERR_INT); u32 err_int = I915_READ(GEN7_ERR_INT);
enum pipe pipe;
if (err_int & ERR_INT_POISON) if (err_int & ERR_INT_POISON)
DRM_ERROR("Poison interrupt\n"); DRM_ERROR("Poison interrupt\n");
if (err_int & ERR_INT_FIFO_UNDERRUN_A) for_each_pipe(pipe) {
if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false)) if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n"); if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
false))
DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
pipe_name(pipe));
}
if (err_int & ERR_INT_FIFO_UNDERRUN_B) if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false)) if (IS_IVYBRIDGE(dev))
DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n"); ivb_pipe_crc_update(dev, pipe);
else
if (err_int & ERR_INT_FIFO_UNDERRUN_C) hsw_pipe_crc_update(dev, pipe);
if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false)) }
DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n"); }
if (err_int & ERR_INT_PIPE_CRC_DONE_A)
ivb_pipe_crc_update(dev, PIPE_A);
if (err_int & ERR_INT_PIPE_CRC_DONE_B)
ivb_pipe_crc_update(dev, PIPE_B);
if (err_int & ERR_INT_PIPE_CRC_DONE_C)
ivb_pipe_crc_update(dev, PIPE_C);
I915_WRITE(GEN7_ERR_INT, err_int); I915_WRITE(GEN7_ERR_INT, err_int);
} }

1
drivers/gpu/drm/i915/i915_reg.h
View File

@ -728,6 +728,7 @@
#define ERR_INT_PIPE_CRC_DONE_B (1<<5) #define ERR_INT_PIPE_CRC_DONE_B (1<<5)
#define ERR_INT_FIFO_UNDERRUN_B (1<<3) #define ERR_INT_FIFO_UNDERRUN_B (1<<3)
#define ERR_INT_PIPE_CRC_DONE_A (1<<2) #define ERR_INT_PIPE_CRC_DONE_A (1<<2)
#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3))
#define ERR_INT_FIFO_UNDERRUN_A (1<<0) #define ERR_INT_FIFO_UNDERRUN_A (1<<0)
#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3))