Samsung clk driver updates for v4.3
- add cpu clock configuration data and instantiate cpu clock for exynos3250, 4210, 4412 and 5250 SoCs to support Samsung specific cpu-clock type * Note this branch has been provided to clk tree as a topic branch -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIbBAABAgAGBQJVzN8oAAoJEA0Cl+kVi2xqV8cP9Rv2PhHGA9HE+bNMWeB3FqkE +CfGPhjhwLOzWdfYCaKCWiTYtABU9X0TBmfWEPsmB0sDCfFcbkaeEkNiGHnxIEfr XCoE/zGg7Wr49PxuNvBsr3YoysA+2B0hchito1GT5qZts35NZdjo79KbTfLxRuC4 E8XPmpNwWpy9QXVIbo8x0v1IRRUJFe/EssL2HMhpJi1LLxqen4wkAQX7C1Kt4RfP 4OvqSMIz/YgbX7Xvqkk8JfILTYgGVgobUMy7RlJdWh49Pqv0SbSP+lICkXZ6tZAR Pbd6urv6E1H5Su7JwxUHtVpJQ//ycdYKsZ5HLTurczBU0XWZ5RdcN+7TDyk8NdjX B1hWF1Ahummt6imuqGEm8DZjRZ9rGmCnQBV8NrXYXDvRLskyTOF+sUYp6obXf9hr xr2HXYK+qdKuVc88QFrCS0K/ElXTXHRjeQR1aD8ennC9/BcnHNRgYvuikv/Oet91 HcwHRed0761J4dt1TRFs4C8rIYho5TEEmecx9Ewu6xh6Pod7H/g39y5xESoVuiL6 UZNBvtcgUqbGz6UOoZd8MTilIyPFY2QuWUiRGH+ydsItM3GoQZa2t0kI3xwOQwD+ 56AfEqKGJj8Ei+zPwLnTBrT4cPPglRgwX6PAnONAwO1XadyE8q2zRycI3Y5tDP+4 VnI4Q7zDKw9NAZdtMqk= =AWdl -----END PGP SIGNATURE----- Merge tag 'samsung-clk-driver' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/late Samsung clk driver updates for v4.3 - add cpu clock configuration data and instantiate cpu clock for exynos3250, 4210, 4412 and 5250 SoCs to support Samsung specific cpu-clock type * Note this branch has been provided to clk tree as a topic branch * tag 'samsung-clk-driver' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: clk: exynos4x12: add cpu clock configuration data and instantiate cpu clock clk: exynos3250: Add cpu clock configuration data and instaniate cpu clock clk: exynos5250: add cpu clock configuration data and instantiate cpu clock Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
6b0770582d
|
|
@ -19,6 +19,7 @@
|
|||
#include <dt-bindings/clock/exynos3250.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "clk-cpu.h"
|
||||
#include "clk-pll.h"
|
||||
|
||||
#define SRC_LEFTBUS 0x4200
|
||||
|
|
@ -319,8 +320,10 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
|
|||
MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
|
||||
SRC_CPU, 24, 1),
|
||||
MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
|
||||
MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1),
|
||||
MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
|
||||
MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1,
|
||||
CLK_SET_RATE_PARENT, 0),
|
||||
MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
|
||||
CLK_SET_RATE_PARENT, 0),
|
||||
};
|
||||
|
||||
static struct samsung_div_clock div_clks[] __initdata = {
|
||||
|
|
@ -772,6 +775,26 @@ static struct samsung_cmu_info cmu_info __initdata = {
|
|||
.nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),
|
||||
};
|
||||
|
||||
#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \
|
||||
(((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
|
||||
((corem) << 4))
|
||||
#define E3250_CPU_DIV1(hpm, copy) \
|
||||
(((hpm) << 4) | ((copy) << 0))
|
||||
|
||||
static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
|
||||
{ 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
static void __init exynos3250_cmu_init(struct device_node *np)
|
||||
{
|
||||
struct samsung_clk_provider *ctx;
|
||||
|
|
@ -780,6 +803,11 @@ static void __init exynos3250_cmu_init(struct device_node *np)
|
|||
if (!ctx)
|
||||
return;
|
||||
|
||||
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
|
||||
mout_core_p[0], mout_core_p[1], 0x14200,
|
||||
e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),
|
||||
CLK_CPU_HAS_DIV1);
|
||||
|
||||
exynos3_core_down_clock(ctx->reg_base);
|
||||
}
|
||||
CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
|
||||
|
|
|
|||
|
|
@ -1396,6 +1396,45 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
|
|||
{ 0 },
|
||||
};
|
||||
|
||||
static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {
|
||||
{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
|
||||
{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
|
||||
{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
|
||||
{ 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
|
||||
{ 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },
|
||||
{ 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },
|
||||
{ 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
|
||||
{ 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
|
||||
{ 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
|
||||
{ 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
|
||||
{ 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
|
||||
{ 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
|
||||
{ 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
|
||||
{ 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
#define E4412_CPU_DIV1(cores, hpm, copy) \
|
||||
(((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
|
||||
|
||||
static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {
|
||||
{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
|
||||
{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },
|
||||
{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },
|
||||
{ 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), },
|
||||
{ 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), },
|
||||
{ 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), },
|
||||
{ 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), },
|
||||
{ 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), },
|
||||
{ 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), },
|
||||
{ 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
|
||||
{ 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
|
||||
{ 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
|
||||
{ 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
|
||||
{ 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
/* register exynos4 clocks */
|
||||
static void __init exynos4_clk_init(struct device_node *np,
|
||||
enum exynos4_soc soc)
|
||||
|
|
@ -1489,6 +1528,17 @@ static void __init exynos4_clk_init(struct device_node *np,
|
|||
samsung_clk_register_fixed_factor(ctx,
|
||||
exynos4x12_fixed_factor_clks,
|
||||
ARRAY_SIZE(exynos4x12_fixed_factor_clks));
|
||||
if (of_machine_is_compatible("samsung,exynos4412")) {
|
||||
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
|
||||
mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
|
||||
e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
|
||||
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
|
||||
} else {
|
||||
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
|
||||
mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
|
||||
e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d),
|
||||
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
|
||||
}
|
||||
}
|
||||
|
||||
samsung_clk_register_alias(ctx, exynos4_aliases,
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "clk-cpu.h"
|
||||
|
||||
#define APLL_LOCK 0x0
|
||||
#define APLL_CON0 0x100
|
||||
|
|
@ -748,6 +749,32 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
|
|||
VPLL_LOCK, VPLL_CON0, NULL),
|
||||
};
|
||||
|
||||
#define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) \
|
||||
((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
|
||||
((periph) << 12) | ((acp) << 8) | ((cpud) << 4)))
|
||||
#define E5250_CPU_DIV1(hpm, copy) \
|
||||
(((hpm) << 4) | (copy))
|
||||
|
||||
static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {
|
||||
{ 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
|
||||
{ 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
|
||||
{ 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
|
||||
{ 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
|
||||
{ 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
|
||||
{ 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
|
||||
{ 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
|
||||
{ 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
|
||||
{ 900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
|
||||
{ 800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
|
||||
{ 700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
|
||||
{ 600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
|
||||
{ 500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
|
||||
{ 400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
|
||||
{ 300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
|
||||
{ 200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
static const struct of_device_id ext_clk_match[] __initconst = {
|
||||
{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
|
||||
{ },
|
||||
|
|
@ -797,6 +824,10 @@ static void __init exynos5250_clk_init(struct device_node *np)
|
|||
ARRAY_SIZE(exynos5250_div_clks));
|
||||
samsung_clk_register_gate(ctx, exynos5250_gate_clks,
|
||||
ARRAY_SIZE(exynos5250_gate_clks));
|
||||
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
|
||||
mout_cpu_p[0], mout_cpu_p[1], 0x200,
|
||||
exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
|
||||
CLK_CPU_HAS_DIV1);
|
||||
|
||||
/*
|
||||
* Enable arm clock down (in idle) and set arm divider
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@
|
|||
#define CLK_FOUT_VPLL 4
|
||||
#define CLK_FOUT_UPLL 5
|
||||
#define CLK_FOUT_MPLL 6
|
||||
#define CLK_ARM_CLK 7
|
||||
|
||||
/* Muxes */
|
||||
#define CLK_MOUT_MPLL_USER_L 16
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#define CLK_FOUT_CPLL 6
|
||||
#define CLK_FOUT_EPLL 7
|
||||
#define CLK_FOUT_VPLL 8
|
||||
#define CLK_ARM_CLK 9
|
||||
|
||||
/* gate for special clocks (sclk) */
|
||||
#define CLK_SCLK_CAM_BAYER 128
|
||||
|
|
|
|||
Loading…
Reference in New Issue