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clk: exynos5433: Fix parent clocks for FSYS block 

The proper parent clock for FSYS block is "aclk_fsys_200"
according to the Exynos5433 reference manual.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Marek Szyprowski 2016-11-17 12:42:52 +01:00 committed by Sylwester Nawrocki
parent 1001354ca3
commit 9a81188e4c
2 changed files with 4 additions and 4 deletions
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6
Documentation/devicetree/bindings/clock/exynos5433-clock.txt
View File

@ -79,7 +79,7 @@ Required Properties:
Input clocks for fsys clock controller: Input clocks for fsys clock controller:
- oscclk - oscclk
- sclk_ufs_mphy - sclk_ufs_mphy
- div_aclk_fsys_200 - aclk_fsys_200
- sclk_pcie_100_fsys - sclk_pcie_100_fsys
- sclk_ufsunipro_fsys - sclk_ufsunipro_fsys
- sclk_mmc2_fsys - sclk_mmc2_fsys
@ -235,7 +235,7 @@ Example 2: Examples of clock controller nodes are listed below.
clock-names = "oscclk", clock-names = "oscclk",
"sclk_ufs_mphy", "sclk_ufs_mphy",
"div_aclk_fsys_200", "aclk_fsys_200",
"sclk_pcie_100_fsys", "sclk_pcie_100_fsys",
"sclk_ufsunipro_fsys", "sclk_ufsunipro_fsys",
"sclk_mmc2_fsys", "sclk_mmc2_fsys",
@ -245,7 +245,7 @@ Example 2: Examples of clock controller nodes are listed below.
"sclk_usbdrd30_fsys"; "sclk_usbdrd30_fsys";
clocks = <&xxti>, clocks = <&xxti>,
<&cmu_cpif CLK_SCLK_UFS_MPHY>, <&cmu_cpif CLK_SCLK_UFS_MPHY>,
<&cmu_top CLK_DIV_ACLK_FSYS_200>, <&cmu_top CLK_ACLK_FSYS_200>,
<&cmu_top CLK_SCLK_PCIE_100_FSYS>, <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
<&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
<&cmu_top CLK_SCLK_MMC2_FSYS>, <&cmu_top CLK_SCLK_MMC2_FSYS>,

2
drivers/clk/samsung/clk-exynos5433.c
View File

@ -1929,7 +1929,7 @@ CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
/* list of all parent clock list */ /* list of all parent clock list */
PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", }; PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", };
PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", }; PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "aclk_fsys_200", };
PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",}; PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",};
PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",}; PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",};
PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", }; PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", };