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Merge e767b3530a ("Merge tag 'arm-drivers-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc") into android-mainline 

Big arm merge on the way to 5.12-rc1

Resolves conflicts with:
	arch/arm/mach-prima2/rstc.c
	arch/arm64/boot/dts/amlogic/Makefile

Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: I58a576c81f4f78f59111389a472b94c5e751d31d
This commit is contained in:
Greg Kroah-Hartman 2021-02-23 11:54:58 +01:00
parent 600066b974 e767b3530a
commit 9b0dfa3d20
909 changed files with 33924 additions and 26959 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/arm/amlogic.yaml
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@ -151,6 +151,7 @@ properties:
- description: Boards with the Amlogic Meson G12B S922X SoC
items:
- enum:
- azw,gsking-x
- azw,gtking
- azw,gtking-pro
- hardkernel,odroid-n2
@ -163,9 +164,10 @@ properties:
- description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC
items:
- enum:
- seirobotics,sei610
- khadas,vim3l
- hardkernel,odroid-c4
- hardkernel,odroid-hc4
- khadas,vim3l
- seirobotics,sei610
- const: amlogic,sm1
- description: Boards with the Amlogic Meson A1 A113L SoC

42
Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml Normal file
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@ -0,0 +1,42 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-mx-secbus2.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic Meson8/Meson8b/Meson8m2 SECBUS2 register interface
maintainers:
- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
description: |
The Meson8/Meson8b/Meson8m2 SoCs have a register bank called SECBUS2 which
contains registers for various IP blocks such as pin-controller bits for
the BSD_EN and TEST_N GPIOs as well as some AO ARC core control bits.
The registers can be accessed directly when not running in "secure mode".
When "secure mode" is enabled then these registers have to be accessed
through secure monitor calls.
properties:
compatible:
items:
- enum:
- amlogic,meson8-secbus2
- amlogic,meson8b-secbus2
- const: syscon
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
secbus2: system-controller@4000 {
compatible = "amlogic,meson8-secbus2", "syscon";
reg = <0x4000 0x2000>;
};

8
Documentation/devicetree/bindings/arm/arm,scmi.txt
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@ -31,6 +31,14 @@ Optional properties:
- mbox-names: shall be "tx" or "rx" depending on mboxes entries.
- interrupts : when using smc or hvc transports, this optional
property indicates that msg completion by the platform is indicated
by an interrupt rather than by the return of the smc call. This
should not be used except when the platform requires such behavior.
- interrupt-names : if "interrupts" is present, interrupt-names must also
be present and have the value "a2p".
See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
about the generic mailbox controller and client driver bindings.

2
Documentation/devicetree/bindings/arm/atmel-sysregs.txt
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@ -1,7 +1,7 @@
Atmel system registers
Chipid required properties:
- compatible: Should be "atmel,sama5d2-chipid"
- compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid"
- reg : Should contain registers location and length
PIT Timer required properties:

2
Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml
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@ -19,6 +19,8 @@ properties:
oneOf:
- description: BCM4906 based boards
items:
- enum:
- netgear,r8000p
- const: brcm,bcm4906
- const: brcm,bcm4908

1
Documentation/devicetree/bindings/arm/cpus.yaml
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@ -169,6 +169,7 @@ properties:
- qcom,kryo385
- qcom,kryo468
- qcom,kryo485
- qcom,kryo685
- qcom,scorpion
enable-method:

23
Documentation/devicetree/bindings/arm/fsl.yaml
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@ -210,6 +210,7 @@ properties:
- kiebackpeter,imx6q-tpc # K+P i.MX6 Quad TPC Board
- kontron,imx6q-samx6i # Kontron i.MX6 Dual/Quad SMARC Module
- kosagi,imx6q-novena # Kosagi Novena Dual/Quad
- kvg,vicut1q # Kverneland UT1Q board
- logicpd,imx6q-logicpd
- lwn,display5 # Liebherr Display5 i.MX6 Quad Board
- lwn,mccmon6 # Liebherr Monitor6 i.MX6 Quad Board
@ -331,6 +332,7 @@ properties:
- fsl,imx6qp-sabreauto # i.MX6 Quad Plus SABRE Automotive Board
- fsl,imx6qp-sabresd # i.MX6 Quad Plus SABRE Smart Device Board
- karo,imx6qp-tx6qp # Ka-Ro electronics TX6QP-8037 Module
- kvg,vicutp # Kverneland UT1P board
- prt,prtwd3 # Protonic WD3 board
- wand,imx6qp-wandboard # Wandboard i.MX6 QuadPlus Board
- zii,imx6qp-zii-rdu2 # ZII RDU2+ Board
@ -364,7 +366,12 @@ properties:
- fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board
- karo,imx6dl-tx6dl # Ka-Ro electronics TX6U Modules
- kontron,imx6dl-samx6i # Kontron i.MX6 Solo SMARC Module
- kvg,victgo # Kverneland TGO
- kvg,vicut1 # Kverneland UT1 board
- ply,plybas # Plymovent BAS board
- ply,plym2m # Plymovent M2M board
- poslab,imx6dl-savageboard # Poslab SavageBoard Dual
- prt,prtmvt # Protonic MVT board
- prt,prtrvt # Protonic RVT board
- prt,prtvt7 # Protonic VT7 board
- rex,imx6dl-rex-basic # Rex Basic i.MX6 Dual Lite Board
@ -488,6 +495,7 @@ properties:
- karo,imx6ul-tx6ul # Ka-Ro electronics TXUL-0010 Module
- kontron,imx6ul-n6310-som # Kontron N6310 SOM
- kontron,imx6ul-n6311-som # Kontron N6311 SOM
- prt,prti6g # Protonic PRTI6G Board
- technexion,imx6ul-pico-dwarf # TechNexion i.MX6UL Pico-Dwarf
- technexion,imx6ul-pico-hobbit # TechNexion i.MX6UL Pico-Hobbit
- technexion,imx6ul-pico-pi # TechNexion i.MX6UL Pico-Pi
@ -670,8 +678,12 @@ properties:
items:
- enum:
- beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit
- boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board
- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
- fsl,imx8mm-evk # i.MX8MM EVK Board
- gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
- kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM
- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
- const: fsl,imx8mm
@ -691,6 +703,7 @@ properties:
- description: i.MX8MN based Boards
items:
- enum:
- beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit
- fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
- const: fsl,imx8mn
@ -707,6 +720,12 @@ properties:
- fsl,imx8mp-evk # i.MX8MP EVK Board
- const: fsl,imx8mp
- description: PHYTEC phyCORE-i.MX8MP SoM based boards
items:
- const: phytec,imx8mp-phyboard-pollux-rdk # phyBOARD-Pollux RDK
- const: phytec,imx8mp-phycore-som # phyCORE-i.MX8MP SoM
- const: fsl,imx8mp
- description: i.MX8MQ based Boards
items:
- enum:
@ -724,6 +743,7 @@ properties:
- enum:
- purism,librem5r2 # Purism Librem5 phone "Chestnut"
- purism,librem5r3 # Purism Librem5 phone "Dogwood"
- purism,librem5r4 # Purism Librem5 phone "Evergreen"
- const: purism,librem5
- const: fsl,imx8mq
@ -834,10 +854,12 @@ properties:
Kontron SMARC-sAL28 board on the SMARC Eval Carrier 2.0
items:
- enum:
- kontron,sl28-var1-ads2
- kontron,sl28-var2-ads2
- kontron,sl28-var3-ads2
- kontron,sl28-var4-ads2
- enum:
- kontron,sl28-var1
- kontron,sl28-var2
- kontron,sl28-var3
- kontron,sl28-var4
@ -848,6 +870,7 @@ properties:
Kontron SMARC-sAL28 board (on a generic/undefined carrier)
items:
- enum:
- kontron,sl28-var1
- kontron,sl28-var2
- kontron,sl28-var3
- kontron,sl28-var4

4
Documentation/devicetree/bindings/arm/mediatek.yaml
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@ -120,7 +120,9 @@ properties:
- const: mediatek,mt8183
- description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
items:
- const: google,krane-sku176
- enum:
- google,krane-sku0
- google,krane-sku176
- const: google,krane
- const: mediatek,mt8183

1
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
View File

@ -24,6 +24,7 @@ properties:
- qcom,sc7180-llcc
- qcom,sdm845-llcc
- qcom,sm8150-llcc
- qcom,sm8250-llcc
reg:
items:

12
Documentation/devicetree/bindings/arm/qcom.yaml
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@ -40,7 +40,9 @@ description: |
sdm630
sdm660
sdm845
sdx55
sm8250
sm8350
The 'board' element must be one of the following strings:
@ -167,6 +169,11 @@ properties:
- xiaomi,lavender
- const: qcom,sdm660
- items:
- enum:
- qcom,sdx55-mtp
- const: qcom,sdx55
- items:
- enum:
- qcom,ipq6018-cp01-c1
@ -178,6 +185,11 @@ properties:
- qcom,sm8250-mtp
- const: qcom,sm8250
- items:
- enum:
- qcom,sm8350-mtp
- const: qcom,sm8350
additionalProperties: true
...

2
Documentation/devicetree/bindings/arm/renesas.yaml
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@ -130,6 +130,7 @@ properties:
- description: RZ/G2N (R8A774B1)
items:
- enum:
- beacon,beacon-rzg2n # Beacon EmbeddedWorks RZ/G2N Kit
- hoperun,hihope-rzg2n # HopeRun HiHope RZ/G2N platform
- const: renesas,r8a774b1
@ -154,6 +155,7 @@ properties:
- description: RZ/G2H (R8A774E1)
items:
- enum:
- beacon,beacon-rzg2h # Beacon EmbeddedWorks RZ/G2H Kit
- hoperun,hihope-rzg2h # HopeRun HiHope RZ/G2H platform
- const: renesas,r8a774e1

5
Documentation/devicetree/bindings/arm/rockchip.yaml
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@ -467,6 +467,11 @@ properties:
- const: radxa,rockpi4
- const: rockchip,rk3399
- description: Radxa ROCK Pi E
items:
- const: radxa,rockpi-e
- const: rockchip,rk3328
- description: Radxa ROCK Pi N8
items:
- const: radxa,rockpi-n8

30
Documentation/devicetree/bindings/arm/sirf.yaml
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@ -1,30 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sirf.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CSR SiRFprimaII and SiRFmarco device tree bindings.
maintainers:
- Binghua Duan <binghua.duan@csr.com>
- Barry Song <Baohua.Song@csr.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- const: sirf,atlas6-cb
- const: sirf,atlas6
- items:
- const: sirf,atlas7-cb
- const: sirf,atlas7
- items:
- const: sirf,prima2-cb
- const: sirf,prima2
additionalProperties: true
...

46
Documentation/devicetree/bindings/arm/ste-u300.txt
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@ -1,46 +0,0 @@
ST-Ericsson U300 Device Tree Bindings
For various board the "board" node may contain specific properties
that pertain to this particular board, such as board-specific GPIOs
or board power regulator supplies.
Required root node property:
compatible="stericsson,u300";
Required node: syscon
This contains the system controller.
- compatible: must be "stericsson,u300-syscon".
- reg: the base address and size of the system controller.
Boards with the U300 SoC include:
S365 "Small Board U365":
Required node: s365
This contains the board-specific information.
- compatible: must be "stericsson,s365".
- vana15-supply: the regulator supplying the 1.5V to drive the
board.
- syscon: a pointer to the syscon node so we can access the
syscon registers to set the board as self-powered.
Example:
/ {
model = "ST-Ericsson U300";
compatible = "stericsson,u300";
#address-cells = <1>;
#size-cells = <1>;
s365 {
compatible = "stericsson,s365";
vana15-supply = <&ab3100_ldo_d_reg>;
syscon = <&syscon>;
};
syscon: syscon@c0011000 {
compatible = "stericsson,u300-syscon";
reg = <0xc0011000 0x1000>;
};
};

19
Documentation/devicetree/bindings/arm/sunxi.yaml
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@ -657,7 +657,8 @@ properties:
- description: Pine64 PineCube
items:
- const: pine64,pinecube
- const: allwinner,sun8i-s3
- const: sochip,s3
- const: allwinner,sun8i-v3
- description: Pine64 PineH64 model A
items:
@ -683,23 +684,31 @@ properties:
- description: Pine64 PinePhone Developer Batch (1.0)
items:
- const: pine64,pinephone-1.0
- const: pine64,pinephone
- const: allwinner,sun50i-a64
- description: Pine64 PinePhone Braveheart (1.1)
items:
- const: pine64,pinephone-1.1
- const: pine64,pinephone
- const: allwinner,sun50i-a64
- description: Pine64 PinePhone (1.2)
items:
- const: pine64,pinephone-1.2
- const: pine64,pinephone
- const: allwinner,sun50i-a64
- description: Pine64 PineTab
- description: Pine64 PineTab, Development Sample
items:
- const: pine64,pinetab
- const: allwinner,sun50i-a64
- description: Pine64 PineTab, Early Adopter's batch (and maybe later ones)
items:
- const: pine64,pinetab-early-adopter
- const: allwinner,sun50i-a64
- description: Pine64 SoPine Baseboard
items:
- const: pine64,sopine-baseboard
@ -777,6 +786,12 @@ properties:
- const: sinlinx,sina33
- const: allwinner,sun8i-a33
- description: SL631 Action Camera with IMX179
items:
- const: allwinner,sl631-imx179
- const: allwinner,sl631
- const: allwinner,sun8i-v3
- description: Tanix TX6
items:
- const: oranth,tanix-tx6

8
Documentation/devicetree/bindings/arm/tegra.yaml
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@ -120,10 +120,18 @@ properties:
items:
- const: nvidia,p3668-0000
- const: nvidia,tegra194
- description: Jetson Xavier NX (eMMC)
items:
- const: nvidia,p3668-0001
- const: nvidia,tegra194
- description: Jetson Xavier NX Developer Kit
items:
- const: nvidia,p3509-0000+p3668-0000
- const: nvidia,tegra194
- description: Jetson Xavier NX Developer Kit (eMMC)
items:
- const: nvidia,p3509-0000+p3668-0001
- const: nvidia,tegra194
- items:
- enum:
- nvidia,tegra234-vdk

6
Documentation/devicetree/bindings/arm/xilinx.yaml
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@ -22,6 +22,9 @@ properties:
- adapteva,parallella
- digilent,zynq-zybo
- digilent,zynq-zybo-z7
- ebang,ebaz4205
- myir,zynq-zturn-v5
- myir,zynq-zturn
- xlnx,zynq-cc108
- xlnx,zynq-zc702
- xlnx,zynq-zc706
@ -91,6 +94,7 @@ properties:
items:
- enum:
- xlnx,zynqmp-zcu104-revA
- xlnx,zynqmp-zcu104-revC
- xlnx,zynqmp-zcu104-rev1.0
- const: xlnx,zynqmp-zcu104
- const: xlnx,zynqmp
@ -107,7 +111,7 @@ properties:
items:
- enum:
- xlnx,zynqmp-zcu111-revA
- xlnx,zynqmp-zcu11-rev1.0
- xlnx,zynqmp-zcu111-rev1.0
- const: xlnx,zynqmp-zcu111
- const: xlnx,zynqmp

30
Documentation/devicetree/bindings/arm/zte,sysctrl.txt
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@ -1,30 +0,0 @@
ZTE sysctrl Registers
Registers for 'zte,zx296702' SoC:
System management required properties:
- compatible = "zte,sysctrl"
Low power management required properties:
- compatible = "zte,zx296702-pcu"
Bus matrix required properties:
- compatible = "zte,zx-bus-matrix"
Registers for 'zte,zx296718' SoC:
System management required properties:
- compatible = "zte,zx296718-aon-sysctrl"
- compatible = "zte,zx296718-sysctrl"
Example:
aon_sysctrl: aon-sysctrl@116000 {
compatible = "zte,zx296718-aon-sysctrl", "syscon";
reg = <0x116000 0x1000>;
};
sysctrl: sysctrl@1463000 {
compatible = "zte,zx296718-sysctrl", "syscon";
reg = <0x1463000 0x1000>;
};

28
Documentation/devicetree/bindings/arm/zte.yaml
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@ -1,28 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/zte.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ZTE platforms device tree bindings
maintainers:
- Jun Nie <jun.nie@linaro.org>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- enum:
- zte,zx296702-ad1
- const: zte,zx296702
- items:
- enum:
- zte,zx296718-evb
- const: zte,zx296718
additionalProperties: true
...

4
Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml
View File

@ -21,7 +21,9 @@ properties:
oneOf:
- const: allwinner,sun8i-a23-rsb
- items:
- const: allwinner,sun8i-a83t-rsb
- enum:
- allwinner,sun8i-a83t-rsb
- allwinner,sun50i-h616-rsb
- const: allwinner,sun8i-a23-rsb
reg:

40
Documentation/devicetree/bindings/c6x/clocks.txt
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@ -1,40 +0,0 @@
C6X PLL Clock Controllers
-------------------------
This is a first-cut support for the SoC clock controllers. This is still
under development and will probably change as the common device tree
clock support is added to the kernel.
Required properties:
- compatible: "ti,c64x+pll"
May also have SoC-specific value to support SoC-specific initialization
in the driver. One of:
"ti,c6455-pll"
"ti,c6457-pll"
"ti,c6472-pll"
"ti,c6474-pll"
- reg: base address and size of register area
- clock-frequency: input clock frequency in hz
Optional properties:
- ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
- ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
- ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
Example:
clock-controller@29a0000 {
compatible = "ti,c6472-pll", "ti,c64x+pll";
reg = <0x029a0000 0x200>;
clock-frequency = <25000000>;
ti,c64x+pll-bypass-delay = <200>;
ti,c64x+pll-reset-delay = <12000>;
ti,c64x+pll-lock-delay = <80000>;
};

127
Documentation/devicetree/bindings/c6x/dscr.txt
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@ -1,127 +0,0 @@
Device State Configuration Registers
------------------------------------
TI C6X SoCs contain a region of miscellaneous registers which provide various
function for SoC control or status. Details vary considerably among from SoC
to SoC with no two being alike.
In general, the Device State Configuration Registers (DSCR) will provide one or
more configuration registers often protected by a lock register where one or
more key values must be written to a lock register in order to unlock the
configuration register for writes. These configuration register may be used to
enable (and disable in some cases) SoC pin drivers, select peripheral clock
sources (internal or pin), etc. In some cases, a configuration register is
write once or the individual bits are write once. In addition to device config,
the DSCR block may provide registers which are used to reset peripherals,
provide device ID information, provide ethernet MAC addresses, as well as other
miscellaneous functions.
For device state control (enable/disable), each device control is assigned an
id which is used by individual device drivers to control the state as needed.
Required properties:
- compatible: must be "ti,c64x+dscr"
- reg: register area base and size
Optional properties:
NOTE: These are optional in that not all SoCs will have all properties. For
SoCs which do support a given property, leaving the property out of the
device tree will result in reduced functionality or possibly driver
failure.
- ti,dscr-devstat
offset of the devstat register
- ti,dscr-silicon-rev
offset, start bit, and bitsize of silicon revision field
- ti,dscr-rmii-resets
offset and bitmask of RMII reset field. May have multiple tuples if more
than one ethernet port is available.
- ti,dscr-locked-regs
possibly multiple tuples describing registers which are write protected by
a lock register. Each tuple consists of the register offset, lock register
offsset, and the key value used to unlock the register.
- ti,dscr-kick-regs
offset and key values of two "kick" registers used to write protect other
registers in DSCR. On SoCs using kick registers, the first key must be
written to the first kick register and the second key must be written to
the second register before other registers in the area are write-enabled.
- ti,dscr-mac-fuse-regs
MAC addresses are contained in two registers. Each element of a MAC address
is contained in a single byte. This property has two tuples. Each tuple has
a register offset and four cells representing bytes in the register from
most significant to least. The value of these four cells is the MAC byte
index (1-6) of the byte within the register. A value of 0 means the byte
is unused in the MAC address.
- ti,dscr-devstate-ctl-regs
This property describes the bitfields used to control the state of devices.
Each tuple describes a range of identical bitfields used to control one or
more devices (one bitfield per device). The layout of each tuple is:
start_id num_ids reg enable disable start_bit nbits
Where:
start_id is device id for the first device control in the range
num_ids is the number of device controls in the range
reg is the offset of the register holding the control bits
enable is the value to enable a device
disable is the value to disable a device (0xffffffff if cannot disable)
start_bit is the bit number of the first bit in the range
nbits is the number of bits per device control
- ti,dscr-devstate-stat-regs
This property describes the bitfields used to provide device state status
for device states controlled by the DSCR. Each tuple describes a range of
identical bitfields used to provide status for one or more devices (one
bitfield per device). The layout of each tuple is:
start_id num_ids reg enable disable start_bit nbits
Where:
start_id is device id for the first device status in the range
num_ids is the number of devices covered by the range
reg is the offset of the register holding the status bits
enable is the value indicating device is enabled
disable is the value indicating device is disabled
start_bit is the bit number of the first bit in the range
nbits is the number of bits per device status
- ti,dscr-privperm
Offset and default value for register used to set access privilege for
some SoC devices.
Example:
device-state-config-regs@2a80000 {
compatible = "ti,c64x+dscr";
reg = <0x02a80000 0x41000>;
ti,dscr-devstat = <0>;
ti,dscr-silicon-rev = <8 28 0xf>;
ti,dscr-rmii-resets = <0x40020 0x00040000>;
ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
ti,dscr-devstate-ctl-regs =
<0 12 0x40008 1 0 0 2
12 1 0x40008 3 0 30 2
13 2 0x4002c 1 0xffffffff 0 1>;
ti,dscr-devstate-stat-regs =
<0 10 0x40014 1 0 0 3
10 2 0x40018 1 0 0 3>;
ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
0x704 5 6 0 0>;
ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
ti,dscr-kick-regs = <0x38 0x83E70B13
0x3c 0x95A4F1E0>;
};

62
Documentation/devicetree/bindings/c6x/emifa.txt
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@ -1,62 +0,0 @@
External Memory Interface
-------------------------
The emifa node describes a simple external bus controller found on some C6X
SoCs. This interface provides external busses with a number of chip selects.
Required properties:
- compatible: must be "ti,c64x+emifa", "simple-bus"
- reg: register area base and size
- #address-cells: must be 2 (chip-select + offset)
- #size-cells: must be 1
- ranges: mapping from EMIFA space to parent space
Optional properties:
- ti,dscr-dev-enable: Device ID if EMIF is enabled/disabled from DSCR
- ti,emifa-burst-priority:
Number of memory transfers after which the EMIF will elevate the priority
of the oldest command in the command FIFO. Setting this field to 255
disables this feature, thereby allowing old commands to stay in the FIFO
indefinitely.
- ti,emifa-ce-config:
Configuration values for each of the supported chip selects.
Example:
emifa@70000000 {
compatible = "ti,c64x+emifa", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x70000000 0x100>;
ranges = <0x2 0x0 0xa0000000 0x00000008
0x3 0x0 0xb0000000 0x00400000
0x4 0x0 0xc0000000 0x10000000
0x5 0x0 0xD0000000 0x10000000>;
ti,dscr-dev-enable = <13>;
ti,emifa-burst-priority = <255>;
ti,emifa-ce-config = <0x00240120
0x00240120
0x00240122
0x00240122>;
flash@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x3 0x0 0x400000>;
bank-width = <1>;
device-width = <1>;
partition@0 {
reg = <0x0 0x400000>;
label = "NOR";
};
};
};
This shows a flash chip attached to chip select 3.

28
Documentation/devicetree/bindings/c6x/soc.txt
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@ -1,28 +0,0 @@
C6X System-on-Chip
------------------
Required properties:
- compatible: "simple-bus"
- #address-cells: must be 1
- #size-cells: must be 1
- ranges
Optional properties:
- model: specific SoC model
- nodes for IP blocks within SoC
Example:
soc {
compatible = "simple-bus";
model = "tms320c6455";
#address-cells = <1>;
#size-cells = <1>;
ranges;
...
};

19
Documentation/devicetree/bindings/display/panel/panel-simple.yaml
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@ -105,26 +105,27 @@ properties:
- dlc,dlc1010gig
# Emerging Display Technology Corp. 3.5" QVGA TFT LCD panel
- edt,et035012dm6
# Emerging Display Technology Corp. 5.7" VGA TFT LCD panel
- edt,et057090dhu
- edt,et070080dh6
# Emerging Display Technology Corp. 480x272 TFT Display with capacitive touch
- edt,etm043080dh6gp
# Emerging Display Technology Corp. 480x272 TFT Display
- edt,etm0430g0dh6
# Emerging Display Technology Corp. 5.7" VGA TFT LCD panel
- edt,et057090dhu
# Emerging Display Technology Corp. WVGA TFT Display with capacitive touch
- edt,etm070080dh6
# Emerging Display Technology Corp. WVGA TFT Display with capacitive touch
- edt,etm0700g0dh6
# Emerging Display Technology Corp. WVGA TFT Display with capacitive touch
# Same as ETM0700G0DH6 but with inverted pixel clock.
- edt,etm070080bdh6
# Emerging Display Technology Corp. WVGA TFT Display with capacitive touch
# Same timings as the ETM0700G0DH6, but with resistive touch.
- edt,etm070080dh6
# Emerging Display Technology Corp. WVGA TFT Display with capacitive touch
# Same display as the ETM0700G0BDH6, but with changed hardware for the
# backlight and the touch interface.
- edt,etm070080edh6
- edt,etm0700g0bdh6
# Emerging Display Technology Corp. WVGA TFT Display with capacitive touch
# Same timings as the ETM0700G0DH6, but with resistive touch.
- edt,etm070080dh6
- edt,etm0700g0dh6
- edt,etm0700g0edh6
# Evervision Electronics Co. Ltd. VGG804821 5.0" WVGA TFT LCD Panel
- evervision,vgg804821
# Foxlink Group 5" WVGA TFT LCD panel
@ -173,6 +174,8 @@ properties:
- koe,tx26d202vm0bwa
# Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel
- koe,tx31d200vm0baa
# Kyocera Corporation 7" WVGA (800x480) transmissive color TFT
- kyo,tcg070wvlq
# Kyocera Corporation 12.1" XGA (1024x768) TFT LCD panel
- kyo,tcg121xglp
# LeMaker BL035-RGB-002 3.5" QVGA TFT LCD panel

2
Documentation/devicetree/bindings/firmware/qcom,scm.txt
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@ -22,6 +22,8 @@ Required properties:
* "qcom,scm-sc7180"
* "qcom,scm-sdm845"
* "qcom,scm-sm8150"
* "qcom,scm-sm8250"
* "qcom,scm-sm8350"
and:
* "qcom,scm"
- clocks: Specifies clocks needed by the SCM interface, if any:

3
Documentation/devicetree/bindings/gpio/mrvl-gpio.yaml
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@ -82,8 +82,7 @@ properties:
'#gpio-cells':
const: 2
gpio-ranges:
maxItems: 1
gpio-ranges: true
interrupts: true

12
Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml
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@ -46,10 +46,14 @@ description: |
properties:
compatible:
enum:
- x-powers,axp209-adc
- x-powers,axp221-adc
- x-powers,axp813-adc
oneOf:
- const: x-powers,axp209-adc
- const: x-powers,axp221-adc
- const: x-powers,axp813-adc
- items:
- const: x-powers,axp803-adc
- const: x-powers,axp813-adc
"#io-channel-cells":
const: 1

3
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
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@ -29,6 +29,9 @@ properties:
- items:
- const: allwinner,sun8i-a83t-r-intc
- const: allwinner,sun6i-a31-r-intc
- items:
- const: allwinner,sun8i-v3s-nmi
- const: allwinner,sun9i-a80-nmi
- const: allwinner,sun9i-a80-nmi
- items:
- const: allwinner,sun50i-a64-r-intc

103
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@ -1,103 +0,0 @@
C6X Interrupt Chips
-------------------
* C64X+ Core Interrupt Controller
The core interrupt controller provides 16 prioritized interrupts to the
C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
sources coming from outside the core.
Required properties:
--------------------
- compatible: Should be "ti,c64x+core-pic";
- #interrupt-cells: <1>
Interrupt Specifier Definition
------------------------------
Single cell specifying the core interrupt priority level (4-15) where
4 is highest priority and 15 is lowest priority.
Example
-------
core_pic: interrupt-controller@0 {
interrupt-controller;
#interrupt-cells = <1>;
compatible = "ti,c64x+core-pic";
};
* C64x+ Megamodule Interrupt Controller
The megamodule PIC consists of four interrupt mupliplexers each of which
combine up to 32 interrupt inputs into a single interrupt output which
may be cascaded into the core interrupt controller. The megamodule PIC
has a total of 12 outputs cascading into the core interrupt controller.
One for each core interrupt priority level. In addition to the combined
interrupt sources, individual megamodule interrupts may be cascaded to
the core interrupt controller. When an individual interrupt is cascaded,
it is no longer handled through a megamodule interrupt combiner and is
considered to have the core interrupt controller as the parent.
Required properties:
--------------------
- compatible: "ti,c64x+megamod-pic"
- interrupt-controller
- #interrupt-cells: <1>
- reg: base address and size of register area
- interrupts: This should have four cells; one for each interrupt combiner.
The cells contain the core priority interrupt to which the
corresponding combiner output is wired.
Optional properties:
--------------------
- ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
priority interrupts. The first cell corresponds to
core priority 4 and the last cell corresponds to
core priority 15. The value of each cell is the
megamodule interrupt source which is MUXed to
the core interrupt corresponding to the cell
position. Allowed values are 4 - 127. Mapping for
interrupts 0 - 3 (combined interrupt sources) are
ignored.
Interrupt Specifier Definition
------------------------------
Single cell specifying the megamodule interrupt source (4-127). Note that
interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
use the core interrupt controller as their parent and the specifier will
be the core priority level, not the megamodule interrupt number.
Examples
--------
megamod_pic: interrupt-controller@1800000 {
compatible = "ti,c64x+megamod-pic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x1800000 0x1000>;
interrupt-parent = <&core_pic>;
interrupts = < 12 13 14 15 >;
};
This is a minimal example where all individual interrupts go through a
combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped
to interrupt 13, etc.
megamod_pic: interrupt-controller@1800000 {
compatible = "ti,c64x+megamod-pic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x1800000 0x1000>;
interrupt-parent = <&core_pic>;
interrupts = < 12 13 14 15 >;
ti,c64x+megamod-pic-mux = < 0 0 0 0
32 0 0 0
0 0 0 0 >;
};
This the same as the first example except that megamodule interrupt 32 is
mapped directly to core priority interrupt 8. The node using this interrupt
must set the core controller as its interrupt parent and use 8 in the
interrupt specifier value.

3
Documentation/devicetree/bindings/media/allwinner,sun8i-h3-deinterlace.yaml
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@ -19,6 +19,9 @@ properties:
compatible:
oneOf:
- const: allwinner,sun8i-h3-deinterlace
- items:
- const: allwinner,sun8i-r40-deinterlace
- const: allwinner,sun8i-h3-deinterlace
- items:
- const: allwinner,sun50i-a64-deinterlace
- const: allwinner,sun8i-h3-deinterlace

5
Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml
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@ -23,6 +23,9 @@ properties:
interrupts:
maxItems: 1
power-domains:
maxItems: 1
port:
type: object
additionalProperties: false
@ -75,6 +78,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/marvell,mmp2.h>
#include <dt-bindings/power/marvell,mmp2.h>
camera@d420a000 {
compatible = "marvell,mmp2-ccic";
@ -84,6 +88,7 @@ examples:
clock-names = "axi";
#clock-cells = <0>;
clock-output-names = "mclk";
power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
port {
camera0_0: endpoint {

6
Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml
View File

@ -26,10 +26,14 @@ properties:
compatible:
items:
- enum:
- renesas,r8a774a1-rpc-if # RZ/G2M
- renesas,r8a774b1-rpc-if # RZ/G2N
- renesas,r8a774c0-rpc-if # RZ/G2E
- renesas,r8a774e1-rpc-if # RZ/G2H
- renesas,r8a77970-rpc-if # R-Car V3M
- renesas,r8a77980-rpc-if # R-Car V3H
- renesas,r8a77995-rpc-if # R-Car D3
- const: renesas,rcar-gen3-rpc-if # a generic R-Car gen3 device
- const: renesas,rcar-gen3-rpc-if # a generic R-Car gen3 or RZ/G2 device
reg:
items:

50
Documentation/devicetree/bindings/power/brcm,bcm-pmb.yaml Normal file
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@ -0,0 +1,50 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/brcm,bcm-pmb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom PMB (Power Management Bus) controller
description: This document describes Broadcom's PMB controller. It supports
powering various types of connected devices (e.g. PCIe, USB, SATA).
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
compatible:
enum:
- brcm,bcm4908-pmb
reg:
description: register space of one or more buses
maxItems: 1
big-endian:
$ref: /schemas/types.yaml#/definitions/flag
description: Flag to use for block working in big endian mode.
"#power-domain-cells":
description: cell specifies device ID (see bcm-pmb.h)
const: 1
required:
- reg
- "#power-domain-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/soc/bcm-pmb.h>
pmb: power-controller@802800e0 {
compatible = "brcm,bcm4908-pmb";
reg = <0x802800e0 0x40>;
#power-domain-cells = <1>;
};
foo {
power-domains = <&pmb BCM_PMB_PCIE0>;
};

11
Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
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@ -23,6 +23,7 @@ properties:
compatible:
enum:
- mediatek,mt8167-power-controller
- mediatek,mt8173-power-controller
- mediatek,mt8183-power-controller
- mediatek,mt8192-power-controller
@ -59,6 +60,7 @@ patternProperties:
reg:
description: |
Power domain index. Valid values are defined in:
"include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.
"include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
"include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
"include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
@ -82,6 +84,9 @@ patternProperties:
be specified by order, adding first the BASIC clocks followed by the
SUSBSYS clocks.
domain-supply:
description: domain regulator supply.
mediatek,infracfg:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the device containing the INFRACFG register range.
@ -130,6 +135,9 @@ patternProperties:
be specified by order, adding first the BASIC clocks followed by the
SUSBSYS clocks.
domain-supply:
description: domain regulator supply.
mediatek,infracfg:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the device containing the INFRACFG register range.
@ -178,6 +186,9 @@ patternProperties:
be specified by order, adding first the BASIC clocks followed by the
SUSBSYS clocks.
domain-supply:
description: domain regulator supply.
mediatek,infracfg:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the device containing the INFRACFG register range.

1
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
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@ -19,6 +19,7 @@ properties:
- qcom,msm8916-rpmpd
- qcom,msm8939-rpmpd
- qcom,msm8976-rpmpd
- qcom,msm8994-rpmpd
- qcom,msm8996-rpmpd
- qcom,msm8998-rpmpd
- qcom,qcs404-rpmpd

39
Documentation/devicetree/bindings/reset/brcm,bcm4908-misc-pcie-reset.yaml Normal file
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@ -0,0 +1,39 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/brcm,bcm4908-misc-pcie-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom MISC block PCIe reset controller
description: This document describes reset controller handling PCIe PERST#
signals. On BCM4908 it's a part of the MISC block.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
compatible:
const: brcm,bcm4908-misc-pcie-reset
reg:
maxItems: 1
"#reset-cells":
description: PCIe core id
const: 1
required:
- compatible
- reg
- "#reset-cells"
additionalProperties: false
examples:
- |
reset-controller@ff802644 {
compatible = "brcm,bcm4908-misc-pcie-reset";
reg = <0xff802644 0x04>;
#reset-cells = <1>;
};

44
Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
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@ -1,44 +0,0 @@
Hisilicon System Reset Controller
======================================
Please also refer to reset.txt in this directory for common reset
controller binding usage.
The reset controller registers are part of the system-ctl block on
hi3660 and hi3670 SoCs.
Required properties:
- compatible: should be one of the following:
"hisilicon,hi3660-reset" for HI3660
"hisilicon,hi3670-reset", "hisilicon,hi3660-reset" for HI3670
- hisi,rst-syscon: phandle of the reset's syscon.
- #reset-cells : Specifies the number of cells needed to encode a
reset source. The type shall be a <u32> and the value shall be 2.
Cell #1 : offset of the reset assert control
register from the syscon register base
offset + 4: deassert control register
offset + 8: status control register
Cell #2 : bit position of the reset in the reset control register
Example:
iomcu: iomcu@ffd7e000 {
compatible = "hisilicon,hi3660-iomcu", "syscon";
reg = <0x0 0xffd7e000 0x0 0x1000>;
};
iomcu_rst: iomcu_rst_controller {
compatible = "hisilicon,hi3660-reset";
hisi,rst-syscon = <&iomcu>;
#reset-cells = <2>;
};
Specifying reset lines connected to IP modules
==============================================
example:
i2c0: i2c@..... {
...
resets = <&iomcu_rst 0x20 3>; /* offset: 0x20; bit: 3 */
...
};

77
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@ -0,0 +1,77 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hisilicon System Reset Controller
maintainers:
- Wei Xu <xuwei5@hisilicon.com>
description: |
Please also refer to reset.txt in this directory for common reset
controller binding usage.
The reset controller registers are part of the system-ctl block on
hi3660 and hi3670 SoCs.
properties:
compatible:
oneOf:
- items:
- const: hisilicon,hi3660-reset
- items:
- const: hisilicon,hi3670-reset
- const: hisilicon,hi3660-reset
hisilicon,rst-syscon:
description: phandle of the reset's syscon.
$ref: /schemas/types.yaml#/definitions/phandle
'#reset-cells':
description: |
Specifies the number of cells needed to encode a reset source.
Cell #1 : offset of the reset assert control register from the syscon
register base
offset + 4: deassert control register
offset + 8: status control register
Cell #2 : bit position of the reset in the reset control register
const: 2
required:
- compatible
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/hi3660-clock.h>
iomcu: iomcu@ffd7e000 {
compatible = "hisilicon,hi3660-iomcu", "syscon";
reg = <0xffd7e000 0x1000>;
};
iomcu_rst: iomcu_rst_controller {
compatible = "hisilicon,hi3660-reset";
hisilicon,rst-syscon = <&iomcu>;
#reset-cells = <2>;
};
/* Specifying reset lines connected to IP modules */
i2c@ffd71000 {
compatible = "snps,designware-i2c";
reg = <0xffd71000 0x1000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
resets = <&iomcu_rst 0x20 3>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
status = "disabled";
};
...

42
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@ -1,42 +0,0 @@
CSR SiRFSoC Reset Controller
======================================
Please also refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: Should be "sirf,prima2-rstc" or "sirf,marco-rstc"
- reg: should be register base and length as documented in the
datasheet
- #reset-cells: 1, see below
example:
rstc: reset-controller@88010000 {
compatible = "sirf,prima2-rstc";
reg = <0x88010000 0x1000>;
#reset-cells = <1>;
};
Specifying reset lines connected to IP modules
==============================================
The reset controller(rstc) manages various reset sources. This module provides
reset signals for most blocks in system. Those device nodes should specify the
reset line on the rstc in their resets property, containing a phandle to the
rstc device node and a RESET_INDEX specifying which module to reset, as described
in reset.txt.
For SiRFSoC, RESET_INDEX is just reset_bit defined in SW_RST0 and SW_RST1 registers.
For modules whose rest_bit is in SW_RST0, its RESET_INDEX is 0~31. For modules whose
rest_bit is in SW_RST1, its RESET_INDEX is 32~63.
example:
vpp@90020000 {
compatible = "sirf,prima2-vpp";
reg = <0x90020000 0x10000>;
interrupts = <31>;
clocks = <&clks 35>;
resets = <&rstc 6>;
};

20
Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt
View File

@ -1,20 +0,0 @@
ZTE zx2967 SoCs Reset Controller
=======================================
Please also refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: should be one of the following.
* zte,zx296718-reset
- reg: physical base address of the controller and length of memory mapped
region.
- #reset-cells: must be 1.
example:
reset: reset-controller@1461060 {
compatible = "zte,zx296718-reset";
reg = <0x01461060 0x8>;
#reset-cells = <1>;
};

1
Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
View File

@ -128,7 +128,6 @@ required:
- compatible
- reg
- interrupts
- clocks
- clock-output-names
additionalProperties: false

2
Documentation/devicetree/bindings/serial/pl011.yaml
View File

@ -19,7 +19,6 @@ select:
contains:
enum:
- arm,pl011
- zte,zx296702-uart
required:
- compatible
@ -30,7 +29,6 @@ properties:
- const: arm,pl011
- const: arm,primecell
- items:
- const: zte,zx296702-uart
- const: arm,primecell
reg:

86
Documentation/devicetree/bindings/soc/imx/imx8m-soc.yaml Normal file
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@ -0,0 +1,86 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/imx8m-soc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8M Series SoC
maintainers:
- Alice Guo <alice.guo@nxp.com>
description: |
NXP i.MX8M series SoCs contain fuse entries from which SoC Unique ID can be
obtained.
select:
properties:
compatible:
contains:
enum:
- fsl,imx8mm
- fsl,imx8mn
- fsl,imx8mp
- fsl,imx8mq
required:
- compatible
patternProperties:
"^soc@[0-9a-f]+$":
type: object
properties:
compatible:
items:
- enum:
- fsl,imx8mm-soc
- fsl,imx8mn-soc
- fsl,imx8mp-soc
- fsl,imx8mq-soc
- const: simple-bus
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
dma-ranges: true
nvmem-cells:
maxItems: 1
description: Phandle to the SOC Unique ID provided by a nvmem node
nvmem-cell-names:
const: soc_unique_id
required:
- compatible
- nvmem-cells
- nvmem-cell-names
additionalProperties:
type: object
additionalProperties: true
examples:
- |
/ {
model = "FSL i.MX8MM EVK board";
compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
#address-cells = <2>;
#size-cells = <2>;
soc@0 {
compatible = "fsl,imx8mm-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
nvmem-cells = <&imx8mm_uid>;
nvmem-cell-names = "soc_unique_id";
};
};
...

1
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt
View File

@ -20,6 +20,7 @@ power-domains.
"qcom,sdm845-aoss-qmp"
"qcom,sm8150-aoss-qmp"
"qcom,sm8250-aoss-qmp"
"qcom,sm8350-aoss-qmp"
- reg:
Usage: required

57
Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt
View File

@ -1,57 +0,0 @@
Qualcomm Shared Memory Manager binding
This binding describes the Qualcomm Shared Memory Manager, used to share data
between various subsystems and OSes in Qualcomm platforms.
- compatible:
Usage: required
Value type: <stringlist>
Definition: must be:
"qcom,smem"
- memory-region:
Usage: required
Value type: <prop-encoded-array>
Definition: handle to memory reservation for main SMEM memory region.
- qcom,rpm-msg-ram:
Usage: required
Value type: <prop-encoded-array>
Definition: handle to RPM message memory resource
- hwlocks:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to a hwspinlock used to protect allocations from
the shared memory
= EXAMPLE
The following example shows the SMEM setup for MSM8974, with a main SMEM region
at 0xfa00000 and the RPM message ram at 0xfc428000:
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
smem_region: smem@fa00000 {
reg = <0xfa00000 0x200000>;
no-map;
};
};
smem@fa00000 {
compatible = "qcom,smem";
memory-region = <&smem_region>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
hwlocks = <&tcsr_mutex 3>;
};
soc {
rpm_msg_ram: memory@fc428000 {
compatible = "qcom,rpm-msg-ram";
reg = <0xfc428000 0x4000>;
};
};

72
Documentation/devicetree/bindings/soc/qcom/qcom,smem.yaml Normal file
View File

@ -0,0 +1,72 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,smem.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Shared Memory Manager binding
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
This binding describes the Qualcomm Shared Memory Manager, used to share data
between various subsystems and OSes in Qualcomm platforms.
properties:
compatible:
const: qcom,smem
memory-region:
maxItems: 1
description: handle to memory reservation for main SMEM memory region.
hwlocks:
maxItems: 1
qcom,rpm-msg-ram:
$ref: /schemas/types.yaml#/definitions/phandle
description: handle to RPM message memory resource
required:
- compatible
- memory-region
- hwlocks
additionalProperties: false
examples:
- |
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
smem_region: smem@fa00000 {
reg = <0xfa00000 0x200000>;
no-map;
};
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
hwlocks = <&tcsr_mutex 3>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rpm_msg_ram: sram@fc428000 {
compatible = "qcom,rpm-msg-ram";
reg = <0xfc428000 0x4000>;
};
};
...

76
Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml
View File

@ -81,6 +81,9 @@ properties:
ranges:
maxItems: 1
dma-ranges:
maxItems: 1
power-domains:
description: |
This property is as per sci-pm-domain.txt.
@ -278,6 +281,9 @@ patternProperties:
that is common to all the PRU cores. This should be represented as an
interrupt-controller node.
allOf:
- $ref: /schemas/interrupt-controller/ti,pruss-intc.yaml#
type: object
mdio@[a-f0-9]+$:
@ -299,6 +305,9 @@ patternProperties:
present on K3 SoCs have additional auxiliary PRU cores with slightly
different IP integration.
allOf:
- $ref: /schemas/remoteproc/ti,pru-rproc.yaml#
type: object
required:
@ -371,6 +380,36 @@ examples:
reg = <0x32000 0x58>;
};
pruss_intc: interrupt-controller@20000 {
compatible = "ti,pruss-intc";
reg = <0x20000 0x2000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <20 21 22 23 24 25 26 27>;
interrupt-names = "host_intr0", "host_intr1",
"host_intr2", "host_intr3",
"host_intr4", "host_intr5",
"host_intr6", "host_intr7";
};
pru0: pru@34000 {
compatible = "ti,am3356-pru";
reg = <0x34000 0x2000>,
<0x22000 0x400>,
<0x22400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am335x-pru0-fw";
};
pru1: pru@38000 {
compatible = "ti,am3356-pru";
reg = <0x38000 0x2000>,
<0x24000 0x400>,
<0x24400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am335x-pru1-fw";
};
pruss_mdio: mdio@32400 {
compatible = "ti,davinci_mdio";
reg = <0x32400 0x90>;
@ -425,6 +464,43 @@ examples:
reg = <0x32000 0x58>;
};
pruss1_intc: interrupt-controller@20000 {
compatible = "ti,pruss-intc";
reg = <0x20000 0x2000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host_intr0", "host_intr1",
"host_intr2", "host_intr3",
"host_intr4",
"host_intr6", "host_intr7";
ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
};
pru1_0: pru@34000 {
compatible = "ti,am4376-pru";
reg = <0x34000 0x3000>,
<0x22000 0x400>,
<0x22400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am437x-pru1_0-fw";
};
pru1_1: pru@38000 {
compatible = "ti,am4376-pru";
reg = <0x38000 0x3000>,
<0x24000 0x400>,
<0x24400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am437x-pru1_1-fw";
};
pruss1_mdio: mdio@32400 {
compatible = "ti,davinci_mdio";
reg = <0x32400 0x90>;

19
Documentation/devicetree/bindings/soc/zte/pd-2967xx.txt
View File

@ -1,19 +0,0 @@
* ZTE zx2967 family Power Domains
zx2967 family includes support for multiple power domains which are used
to gate power to one or more peripherals on the processor.
Required Properties:
- compatible: should be one of the following.
* zte,zx296718-pcu - for zx296718 power domain.
- reg: physical base address of the controller and length of memory mapped
region.
- #power-domain-cells: Must be 1.
Example:
pcu_domain: pcu@117000 {
compatible = "zte,zx296718-pcu";
reg = <0x00117000 0x1000>;
#power-domain-cells = <1>;
};

25
Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
View File

@ -1,25 +0,0 @@
Xilinx Zynq QSPI controller Device Tree Bindings
-------------------------------------------------------------------
Required properties:
- compatible : Should be "xlnx,zynq-qspi-1.0".
- reg : Physical base address and size of QSPI registers map.
- interrupts : Property with a value describing the interrupt
number.
- clock-names : List of input clock names - "ref_clk", "pclk"
(See clock bindings for details).
- clocks : Clock phandles (see clock bindings for details).
Optional properties:
- num-cs : Number of chip selects used.
Example:
qspi: spi@e000d000 {
compatible = "xlnx,zynq-qspi-1.0";
reg = <0xe000d000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <0 19 4>;
clock-names = "ref_clk", "pclk";
clocks = <&clkc 10>, <&clkc 43>;
num-cs = <1>;
};

59
Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml Normal file
View File

@ -0,0 +1,59 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/xlnx,zynq-qspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq QSPI controller
description:
The Xilinx Zynq QSPI controller is used to access multi-bit serial flash
memory devices.
allOf:
- $ref: "spi-controller.yaml#"
maintainers:
- Michal Simek <michal.simek@xilinx.com>
# Everything else is described in the common file
properties:
compatible:
const: xlnx,zynq-qspi-1.0
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: reference clock
- description: peripheral clock
clock-names:
items:
- const: ref_clk
- const: pclk
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
spi@e000d000 {
compatible = "xlnx,zynq-qspi-1.0";
reg = <0xe000d000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <0 19 4>;
clock-names = "ref_clk", "pclk";
clocks = <&clkc 10>, <&clkc 43>;
num-cs = <1>;
};

1
Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml
View File

@ -49,6 +49,7 @@ properties:
- items:
- const: allwinner,suniv-f1c100s-system-control
- const: allwinner,sun4i-a10-system-control
- const: allwinner,sun50i-h616-system-control
reg:
maxItems: 1

2
Documentation/devicetree/bindings/sram/sram.yaml
View File

@ -72,6 +72,8 @@ patternProperties:
- allwinner,sun4i-a10-sram-d
- allwinner,sun9i-a80-smp-sram
- allwinner,sun50i-a64-sram-c
- amlogic,meson8-ao-arc-sram
- amlogic,meson8b-ao-arc-sram
- amlogic,meson8-smp-sram
- amlogic,meson8b-smp-sram
- amlogic,meson-gxbb-scp-shmem

25
Documentation/devicetree/bindings/timer/ti,c64x+timer64.txt
View File

@ -1,25 +0,0 @@
Timer64
-------
The timer64 node describes C6X event timers.
Required properties:
- compatible: must be "ti,c64x+timer64"
- reg: base address and size of register region
- interrupts: interrupt id
Optional properties:
- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface.
- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer.
Example:
timer0: timer@25e0000 {
compatible = "ti,c64x+timer64";
ti,core-mask = < 0x01 >;
reg = <0x25e0000 0x40>;
interrupt-parent = <&megamod_pic>;
interrupts = < 16 >;
};

1
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
View File

@ -17,6 +17,7 @@ properties:
- qcom,msm8998-dwc3
- qcom,sc7180-dwc3
- qcom,sdm845-dwc3
- qcom,sdx55-dwc3
- const: qcom,dwc3
reg:

12
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -59,6 +59,8 @@ patternProperties:
description: Aeroflex Gaisler AB
"^al,.*":
description: Annapurna Labs
"^alcatel,.*":
description: Alcatel
"^allegro,.*":
description: Allegro DVT
"^allo,.*":
@ -311,6 +313,8 @@ patternProperties:
description: Dyna-Image
"^ea,.*":
description: Embedded Artists AB
"^ebang,.*":
description: Zhejiang Ebang Communication Co., Ltd
"^ebs-systart,.*":
description: EBS-SYSTART GmbH
"^ebv,.*":
@ -467,10 +471,10 @@ patternProperties:
description: Hitex Development Tools
"^holt,.*":
description: Holt Integrated Circuits, Inc.
"^honeywell,.*":
description: Honeywell
"^honestar,.*":
description: Honestar Technologies Co., Ltd.
"^honeywell,.*":
description: Honeywell
"^hoperun,.*":
description: Jiangsu HopeRun Software Co., Ltd.
"^hp,.*":
@ -581,6 +585,8 @@ patternProperties:
description: Kontron S&T AG
"^kosagi,.*":
description: Sutajio Ko-Usagi PTE Ltd.
"^kvg,.*":
description: Kverneland Group
"^kyo,.*":
description: Kyocera Corporation
"^lacie,.*":
@ -866,6 +872,8 @@ patternProperties:
description: PLDA
"^plx,.*":
description: Broadcom Corporation (formerly PLX Technology)
"^ply,.*":
description: Plymovent Group BV
"^pni,.*":
description: PNI Sensor Corporation
"^pocketbook,.*":

1
Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
View File

@ -18,6 +18,7 @@ properties:
- qcom,apss-wdt-qcs404
- qcom,apss-wdt-sc7180
- qcom,apss-wdt-sdm845
- qcom,apss-wdt-sdx55
- qcom,apss-wdt-sm8150
- qcom,kpss-timer
- qcom,kpss-wdt

120
MAINTAINERS
View File

@ -1511,6 +1511,7 @@ ARM/ACTIONS SEMI ARCHITECTURE
M: Andreas Färber <afaerber@suse.de>
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-actions@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/arm/actions.yaml
F: Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
@ -1778,19 +1779,6 @@ F: drivers/net/ethernet/cortina/
F: drivers/pinctrl/pinctrl-gemini.c
F: drivers/rtc/rtc-ftrtc010.c
ARM/CSR SIRFPRIMA2 MACHINE SUPPORT
M: Barry Song <baohua@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux.git
F: arch/arm/boot/dts/prima2*
F: arch/arm/mach-prima2/
F: drivers/clk/sirf/
F: drivers/clocksource/timer-atlas7.c
F: drivers/clocksource/timer-prima2.c
X: drivers/gnss
N: [^a-z]sirf
ARM/CZ.NIC TURRIS MOX SUPPORT
M: Marek Behun <marek.behun@nic.cz>
S: Maintained
@ -1806,13 +1794,6 @@ F: drivers/firmware/turris-mox-rwtm.c
F: drivers/gpio/gpio-moxtet.c
F: include/linux/moxtet.h
ARM/ENERGY MICRO (SILICON LABS) EFM32 SUPPORT
M: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
R: Pengutronix Kernel Team <kernel@pengutronix.de>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
N: efm32
ARM/EZX SMARTPHONES (A780, A910, A1200, E680, ROKR E2 and ROKR E6)
M: Robert Jarzmik <robert.jarzmik@free.fr>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -2155,7 +2136,7 @@ ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT
M: Michael Petchkovsky <mkpetch@internode.on.net>
S: Maintained
ARM/NOMADIK/U300/Ux500 ARCHITECTURES
ARM/NOMADIK/Ux500 ARCHITECTURES
M: Linus Walleij <linus.walleij@linaro.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
@ -2164,35 +2145,23 @@ F: Documentation/devicetree/bindings/arm/ste-*
F: Documentation/devicetree/bindings/arm/ux500.yaml
F: Documentation/devicetree/bindings/arm/ux500/
F: Documentation/devicetree/bindings/i2c/i2c-nomadik.txt
F: Documentation/devicetree/bindings/i2c/i2c-stu300.txt
F: arch/arm/boot/dts/ste-*
F: arch/arm/mach-nomadik/
F: arch/arm/mach-u300/
F: arch/arm/mach-ux500/
F: drivers/clk/clk-nomadik.c
F: drivers/clk/clk-u300.c
F: drivers/clocksource/clksrc-dbx500-prcmu.c
F: drivers/clocksource/timer-u300.c
F: drivers/dma/coh901318*
F: drivers/dma/ste_dma40*
F: drivers/hwspinlock/u8500_hsem.c
F: drivers/i2c/busses/i2c-nomadik.c
F: drivers/i2c/busses/i2c-stu300.c
F: drivers/iio/adc/ab8500-gpadc.c
F: drivers/mfd/ab3100*
F: drivers/mfd/ab8500*
F: drivers/mfd/abx500*
F: drivers/mfd/db8500*
F: drivers/mfd/dbx500*
F: drivers/pinctrl/nomadik/
F: drivers/pinctrl/pinctrl-coh901*
F: drivers/pinctrl/pinctrl-u300.c
F: drivers/rtc/rtc-ab3100.c
F: drivers/rtc/rtc-ab8500.c
F: drivers/rtc/rtc-coh901331.c
F: drivers/rtc/rtc-pl031.c
F: drivers/soc/ux500/
F: drivers/watchdog/coh901327_wdt.c
ARM/NUVOTON NPCM ARCHITECTURE
M: Avi Fishman <avifishman70@gmail.com>
@ -2414,6 +2383,8 @@ F: drivers/*/*s5pv210*
F: drivers/memory/samsung/
F: drivers/soc/samsung/
F: drivers/tty/serial/samsung*
F: include/linux/platform_data/*s3c*
F: include/linux/serial_s3c.h
F: include/linux/soc/samsung/
N: exynos
N: s3c2410
@ -2557,13 +2528,6 @@ F: arch/arm/boot/dts/berlin*
F: arch/arm/mach-berlin/
F: arch/arm64/boot/dts/synaptics/
ARM/TANGO ARCHITECTURE
M: Marc Gonzalez <marc.w.gonzalez@free.fr>
M: Mans Rullgard <mans@mansr.com>
L: linux-arm-kernel@lists.infradead.org
S: Odd Fixes
N: tango
ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -2643,9 +2607,11 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti.git
F: Documentation/devicetree/bindings/arm/toshiba.yaml
F: Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml
F: Documentation/devicetree/bindings/pinctrl/toshiba,tmpv7700-pinctrl.yaml
F: Documentation/devicetree/bindings/watchdog/toshiba,visconti-wdt.yaml
F: arch/arm64/boot/dts/toshiba/
F: drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
F: drivers/pinctrl/visconti/
F: drivers/watchdog/visconti_wdt.c
N: visconti
ARM/UNIPHIER ARCHITECTURE
@ -2725,40 +2691,6 @@ S: Maintained
F: arch/arm/mach-pxa/include/mach/z2.h
F: arch/arm/mach-pxa/z2.c
ARM/ZTE ARCHITECTURE
M: Jun Nie <jun.nie@linaro.org>
M: Shawn Guo <shawnguo@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/arm/zte.yaml
F: Documentation/devicetree/bindings/clock/zx2967*.txt
F: Documentation/devicetree/bindings/dma/zxdma.txt
F: Documentation/devicetree/bindings/gpio/zx296702-gpio.txt
F: Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
F: Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
F: Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt
F: Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt
F: Documentation/devicetree/bindings/soc/zte/
F: Documentation/devicetree/bindings/sound/zte,*.txt
F: Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
F: Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt
F: arch/arm/boot/dts/zx2967*
F: arch/arm/mach-zx/
F: arch/arm64/boot/dts/zte/
F: drivers/clk/zte/
F: drivers/dma/zx_dma.c
F: drivers/gpio/gpio-zx.c
F: drivers/i2c/busses/i2c-zx2967.c
F: drivers/mmc/host/dw_mmc-zx.*
F: drivers/pinctrl/zte/
F: drivers/soc/zte/
F: drivers/thermal/zx2967_thermal.c
F: drivers/watchdog/zx2967_wdt.c
F: include/dt-bindings/clock/zx2967*.h
F: include/dt-bindings/soc/zte,*.h
F: sound/soc/codecs/zx_aud96p22.c
F: sound/soc/zte/
ARM/ZYNQ ARCHITECTURE
M: Michal Simek <michal.simek@xilinx.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -2767,6 +2699,7 @@ W: http://wiki.xilinx.com
T: git https://github.com/Xilinx/linux-xlnx.git
F: Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
F: Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml
F: Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml
F: arch/arm/mach-zynq/
F: drivers/block/xsysace.c
F: drivers/clocksource/timer-cadence-ttc.c
@ -3712,6 +3645,16 @@ L: linux-mips@vger.kernel.org
S: Maintained
F: drivers/firmware/broadcom/*
BROADCOM PMB (POWER MANAGEMENT BUS) DRIVER
M: Rafał Miłecki <rafal@milecki.pl>
M: Florian Fainelli <f.fainelli@gmail.com>
M: bcm-kernel-feedback-list@broadcom.com
L: linux-pm@vger.kernel.org
S: Maintained
T: git git://github.com/broadcom/stblinux.git
F: drivers/soc/bcm/bcm-pmb.c
F: include/dt-bindings/soc/bcm-pmb.h
BROADCOM SPECIFIC AMBA DRIVER (BCMA)
M: Rafał Miłecki <zajec5@gmail.com>
L: linux-wireless@vger.kernel.org
@ -3874,14 +3817,6 @@ F: drivers/irqchip/irq-csky-*
N: csky
K: csky
C6X ARCHITECTURE
M: Mark Salter <msalter@redhat.com>
M: Aurelien Jacquiot <jacquiot.aurelien@gmail.com>
L: linux-c6x-dev@linux-c6x.org
S: Maintained
W: http://www.linux-c6x.org/wiki/index.php/Main_Page
F: arch/c6x/
CA8210 IEEE-802.15.4 RADIO DRIVER
M: Harry Morris <h.morris@cascoda.com>
L: linux-wpan@vger.kernel.org
@ -6089,14 +6024,6 @@ T: git git://anongit.freedesktop.org/drm/drm-misc
F: Documentation/devicetree/bindings/display/xlnx/
F: drivers/gpu/drm/xlnx/
DRM DRIVERS FOR ZTE ZX
M: Shawn Guo <shawnguo@kernel.org>
L: dri-devel@lists.freedesktop.org
S: Maintained
T: git git://anongit.freedesktop.org/drm/drm-misc
F: Documentation/devicetree/bindings/display/zte,vou.txt
F: drivers/gpu/drm/zte/
DRM PANEL DRIVERS
M: Thierry Reding <thierry.reding@gmail.com>
R: Sam Ravnborg <sam@ravnborg.org>
@ -12945,7 +12872,7 @@ S: Orphan
F: drivers/video/fbdev/omap/
OMAP GENERAL PURPOSE MEMORY CONTROLLER SUPPORT
M: Roger Quadros <rogerq@ti.com>
M: Roger Quadros <rogerq@kernel.org>
M: Tony Lindgren <tony@atomide.com>
L: linux-omap@vger.kernel.org
S: Maintained
@ -14035,15 +13962,6 @@ L: linux-input@vger.kernel.org
S: Maintained
F: drivers/hid/hid-picolcd*
PICOXCELL SUPPORT
M: Jamie Iles <jamie@jamieiles.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported
T: git git://github.com/jamieiles/linux-2.6-ji.git
F: arch/arm/boot/dts/picoxcell*
F: arch/arm/mach-picoxcell/
F: drivers/crypto/picoxcell*
PIDFD API
M: Christian Brauner <christian@brauner.io>
L: linux-kernel@vger.kernel.org
@ -17270,6 +17188,7 @@ F: drivers/mfd/syscon.c
SYSTEM CONTROL & POWER/MANAGEMENT INTERFACE (SCPI/SCMI) Message Protocol drivers
M: Sudeep Holla <sudeep.holla@arm.com>
R: Cristian Marussi <cristian.marussi@arm.com>
L: linux-arm-kernel@lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/arm/arm,sc[mp]i.txt
@ -17277,6 +17196,7 @@ F: drivers/clk/clk-sc[mp]i.c
F: drivers/cpufreq/sc[mp]i-cpufreq.c
F: drivers/firmware/arm_scmi/
F: drivers/firmware/arm_scpi.c
F: drivers/regulator/scmi-regulator.c
F: drivers/reset/reset-scmi.c
F: include/linux/sc[mp]i_protocol.h
F: include/trace/events/scmi.h

20
arch/arm/Kconfig
View File

@ -670,10 +670,6 @@ source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/mach-oxnas/Kconfig"
source "arch/arm/mach-picoxcell/Kconfig"
source "arch/arm/mach-prima2/Kconfig"
source "arch/arm/mach-pxa/Kconfig"
source "arch/arm/plat-pxa/Kconfig"
@ -705,12 +701,8 @@ source "arch/arm/mach-stm32/Kconfig"
source "arch/arm/mach-sunxi/Kconfig"
source "arch/arm/mach-tango/Kconfig"
source "arch/arm/mach-tegra/Kconfig"
source "arch/arm/mach-u300/Kconfig"
source "arch/arm/mach-uniphier/Kconfig"
source "arch/arm/mach-ux500/Kconfig"
@ -721,19 +713,9 @@ source "arch/arm/mach-vexpress/Kconfig"
source "arch/arm/mach-vt8500/Kconfig"
source "arch/arm/mach-zx/Kconfig"
source "arch/arm/mach-zynq/Kconfig"
# ARMv7-M architecture
config ARCH_EFM32
bool "Energy Micro efm32"
depends on ARM_SINGLE_ARMV7M
select GPIOLIB
help
Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
processors.
config ARCH_LPC18XX
bool "NXP LPC18xx/LPC43xx"
depends on ARM_SINGLE_ARMV7M
@ -1551,7 +1533,7 @@ config ARM_MODULE_PLTS
config FORCE_MAX_ZONEORDER
int "Maximum zone order"
default "12" if SOC_AM33XX
default "9" if SA1111 || ARCH_EFM32
default "9" if SA1111
default "11"
help
The kernel memory allocator divides physically contiguous memory

95
arch/arm/Kconfig.debug
View File

@ -770,14 +770,6 @@ choice
depends on ARCH_OMAP2PLUS
select DEBUG_OMAP2PLUS_UART
config DEBUG_PICOXCELL_UART
depends on ARCH_PICOXCELL
bool "Use PicoXcell UART for low-level debug"
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on PicoXcell based platforms.
config DEBUG_PXA_UART1
depends on ARCH_PXA
bool "Use PXA UART1 for low-level debug"
@ -1150,32 +1142,6 @@ choice
Say Y here if you want kernel low-level debugging support
on Allwinner A31/A23 based platforms on the R_UART.
config DEBUG_SIRFPRIMA2_UART1
bool "Kernel low-level debugging messages via SiRFprimaII UART1"
depends on ARCH_PRIMA2
select DEBUG_SIRFSOC_UART
help
Say Y here if you want the debug print routines to direct
their output to the uart1 port on SiRFprimaII devices.
config DEBUG_SIRFATLAS7_UART0
bool "Kernel low-level debugging messages via SiRFatlas7 UART0"
depends on ARCH_ATLAS7
select DEBUG_SIRFSOC_UART
help
Say Y here if you want the debug print routines to direct
their output to the uart0 port on SiRFATLAS7 devices.The uart0
is used on SiRFATLAS7 as a extra debug port.sometimes an extra
debug port can be very useful.
config DEBUG_SIRFATLAS7_UART1
bool "Kernel low-level debugging messages via SiRFatlas7 UART1"
depends on ARCH_ATLAS7
select DEBUG_SIRFSOC_UART
help
Say Y here if you want the debug print routines to direct
their output to the uart1 port on SiRFATLAS7 devices.
config DEBUG_SPEAR3XX
bool "Kernel low-level debugging messages via ST SPEAr 3xx/6xx UART"
depends on ARCH_SPEAR3XX || ARCH_SPEAR6XX
@ -1314,14 +1280,6 @@ choice
Say Y here if you want kernel low-level debugging support
on Tegra based platforms.
config DEBUG_U300_UART
bool "Kernel low-level debugging messages via U300 UART0"
depends on ARCH_U300
select DEBUG_UART_PL01X
help
Say Y here if you want the debug print routines to direct
their output to the uart port on U300 devices.
config DEBUG_UX500_UART
depends on ARCH_U8500
bool "Use Ux500 UART for low-level debug"
@ -1387,18 +1345,6 @@ choice
This option selects UART0 on VIA/Wondermedia System-on-a-chip
devices, including VT8500, WM8505, WM8650 and WM8850.
config DEBUG_ZTE_ZX
bool "Use ZTE ZX UART"
select DEBUG_UART_PL01X
depends on ARCH_ZX
help
Say Y here if you are enabling ZTE ZX296702 SOC and need
debug uart support.
This option is preferred over the platform specific
options; the platform specific options are deprecated
and will be soon removed.
config DEBUG_ZYNQ_UART0
bool "Kernel low-level debugging on Xilinx Zynq using UART0"
depends on ARCH_ZYNQ
@ -1456,20 +1402,6 @@ choice
options; the platform specific options are deprecated
and will be soon removed.
config DEBUG_LL_UART_EFM32
bool "Kernel low-level debugging via efm32 UART"
depends on ARCH_EFM32
help
Say Y here if you want the debug print routines to direct
their output to an UART or USART port on efm32 based
machines. Use the following addresses for DEBUG_UART_PHYS:
0x4000c000 | USART0
0x4000c400 | USART1
0x4000c800 | USART2
0x4000e000 | UART0
0x4000e400 | UART1
config DEBUG_LL_UART_PL01X
bool "Kernel low-level debugging via ARM Ltd PL01x Primecell UART"
help
@ -1560,10 +1492,6 @@ config DEBUG_STM32_UART
bool
depends on ARCH_STM32
config DEBUG_SIRFSOC_UART
bool
depends on ARCH_SIRF
config DEBUG_UART_FLOW_CONTROL
bool "Enable flow control (CTS) for the debug UART"
depends on DEBUG_LL
@ -1587,7 +1515,6 @@ config DEBUG_LL_INCLUDE
default "debug/meson.S" if DEBUG_MESON_UARTAO
default "debug/pl01x.S" if DEBUG_LL_UART_PL01X || DEBUG_UART_PL01X
default "debug/exynos.S" if DEBUG_EXYNOS_UART
default "debug/efm32.S" if DEBUG_LL_UART_EFM32
default "debug/icedcc.S" if DEBUG_ICEDCC
default "debug/imx.S" if DEBUG_IMX1_UART || \
DEBUG_IMX25_UART || \
@ -1619,7 +1546,6 @@ config DEBUG_LL_INCLUDE
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4
default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART || DEBUG_S3C64XX_UART
default "debug/s5pv210.S" if DEBUG_S5PV210_UART
default "debug/sirf.S" if DEBUG_SIRFSOC_UART
default "debug/sti.S" if DEBUG_STI_UART
default "debug/stm32.S" if DEBUG_STM32_UART
default "debug/tegra.S" if DEBUG_TEGRA_UART
@ -1653,7 +1579,6 @@ config DEBUG_UART_PHYS
default 0x02531000 if DEBUG_KEYSTONE_UART1
default 0x03010fe0 if ARCH_RPC
default 0x07000000 if DEBUG_SUN9I_UART0
default 0x09405000 if DEBUG_ZTE_ZX
default 0x10009000 if DEBUG_REALVIEW_STD_PORT || \
DEBUG_VEXPRESS_UART0_CA9
default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT
@ -1671,8 +1596,6 @@ config DEBUG_UART_PHYS
default 0x1600d000 if DEBUG_SD5203_UART
default 0x18000300 if DEBUG_BCM_5301X
default 0x18000400 if DEBUG_BCM_HR2
default 0x18010000 if DEBUG_SIRFATLAS7_UART0
default 0x18020000 if DEBUG_SIRFATLAS7_UART1
default 0x18023000 if DEBUG_BCM_IPROC_UART3
default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
default 0x20001000 if DEBUG_HIP01_UART
@ -1682,7 +1605,6 @@ config DEBUG_UART_PHYS
default 0x20201000 if DEBUG_BCM2835
default 0x3e000000 if DEBUG_BCM_KONA_UART
default 0x3f201000 if DEBUG_BCM2836
default 0x4000e400 if DEBUG_LL_UART_EFM32
default 0x40010000 if STM32MP1_DEBUG_UART
default 0x40011000 if STM32F4_DEBUG_UART || STM32F7_DEBUG_UART || \
STM32H7_DEBUG_UART
@ -1717,12 +1639,9 @@ config DEBUG_UART_PHYS
default 0x80010000 if DEBUG_ASM9260_UART
default 0x80070000 if DEBUG_IMX23_UART
default 0x80074000 if DEBUG_IMX28_UART
default 0x80230000 if DEBUG_PICOXCELL_UART
default 0x808c0000 if DEBUG_EP93XX || ARCH_EP93XX
default 0x90020000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
default 0xb0060000 if DEBUG_SIRFPRIMA2_UART1
default 0xb0090000 if DEBUG_VEXPRESS_UART0_CRX
default 0xc0013000 if DEBUG_U300_UART
default 0xc8000000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
default 0xc8000003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
default 0xd0000000 if DEBUG_SPEAR3XX
@ -1768,7 +1687,6 @@ config DEBUG_UART_PHYS
default 0xfffff200 if DEBUG_AT91_RM9200_DBGU
depends on ARCH_EP93XX || \
DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
DEBUG_LL_UART_EFM32 || \
DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \
DEBUG_R7S9210_SCIF2 || DEBUG_R7S9210_SCIF4 || \
@ -1780,7 +1698,7 @@ config DEBUG_UART_PHYS
DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
DEBUG_S3C64XX_UART || \
DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \
DEBUG_DIGICOLOR_UA0 || \
DEBUG_AT91_UART || DEBUG_STM32_UART
config DEBUG_UART_VIRT
@ -1842,7 +1760,6 @@ config DEBUG_UART_VIRT
default 0xfb020000 if DEBUG_OMAP3UART3
default 0xfb042000 if DEBUG_OMAP3UART4
default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
default 0xfc705000 if DEBUG_ZTE_ZX
default 0xfcfe8600 if DEBUG_BCM63XX_UART
default 0xfd000000 if DEBUG_SPEAR3XX || DEBUG_SPEAR13XX
default 0xfd883000 if DEBUG_ALPINE_UART0
@ -1850,7 +1767,6 @@ config DEBUG_UART_VIRT
default 0xfe017000 if DEBUG_MMP_UART2
default 0xfe018000 if DEBUG_MMP_UART3
default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART
default 0xfe230000 if DEBUG_PICOXCELL_UART
default 0xfe300000 if DEBUG_BCM_KONA_UART
default 0xfe800000 if ARCH_IOP32X
default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART
@ -1863,10 +1779,7 @@ config DEBUG_UART_VIRT
default 0xfec03000 if DEBUG_SOCFPGA_CYCLONE5_UART1
default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE
default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE
default 0xfec10000 if DEBUG_SIRFATLAS7_UART0
default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0
default 0xfec20000 if DEBUG_SIRFATLAS7_UART1
default 0xfec60000 if DEBUG_SIRFPRIMA2_UART1
default 0xfec90000 if DEBUG_RK32_UART2
default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1
default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART
@ -1882,7 +1795,6 @@ config DEBUG_UART_VIRT
default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
default 0xfefb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3
default 0xff003000 if DEBUG_U300_UART
default 0xffd01000 if DEBUG_HIP01_UART
default DEBUG_UART_PHYS if !MMU
depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
@ -1890,7 +1802,7 @@ config DEBUG_UART_VIRT
DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
DEBUG_S3C64XX_UART || \
DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \
DEBUG_DIGICOLOR_UA0 || \
DEBUG_AT91_UART || DEBUG_STM32_UART
config DEBUG_UART_8250_SHIFT
@ -1905,8 +1817,7 @@ config DEBUG_UART_8250_WORD
bool "Use 32-bit accesses for 8250 UART"
depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
depends on DEBUG_UART_8250_SHIFT >= 2
default y if DEBUG_PICOXCELL_UART || \
DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_ARRIA10_UART1 || \
default y if DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_ARRIA10_UART1 || \
DEBUG_SOCFPGA_CYCLONE5_UART1 || DEBUG_KEYSTONE_UART0 || \
DEBUG_KEYSTONE_UART1 || DEBUG_ALPINE_UART0 || \
DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \

6
arch/arm/Makefile
View File

@ -168,7 +168,6 @@ machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
machine-$(CONFIG_ARCH_DAVINCI) += davinci
machine-$(CONFIG_ARCH_DIGICOLOR) += digicolor
machine-$(CONFIG_ARCH_DOVE) += dove
machine-$(CONFIG_ARCH_EFM32) += efm32
machine-$(CONFIG_ARCH_EP93XX) += ep93xx
machine-$(CONFIG_ARCH_EXYNOS) += exynos
machine-$(CONFIG_ARCH_FOOTBRIDGE) += footbridge
@ -199,7 +198,6 @@ machine-$(CONFIG_ARCH_OXNAS) += oxnas
machine-$(CONFIG_ARCH_OMAP1) += omap1
machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
machine-$(CONFIG_ARCH_ORION5X) += orion5x
machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell
machine-$(CONFIG_ARCH_PXA) += pxa
machine-$(CONFIG_ARCH_QCOM) += qcom
machine-$(CONFIG_ARCH_RDA) += rda
@ -211,19 +209,15 @@ machine-$(CONFIG_PLAT_SAMSUNG) += s3c
machine-$(CONFIG_ARCH_S5PV210) += s5pv210
machine-$(CONFIG_ARCH_SA1100) += sa1100
machine-$(CONFIG_ARCH_RENESAS) += shmobile
machine-$(CONFIG_ARCH_SIRF) += prima2
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_STI) += sti
machine-$(CONFIG_ARCH_STM32) += stm32
machine-$(CONFIG_ARCH_SUNXI) += sunxi
machine-$(CONFIG_ARCH_TANGO) += tango
machine-$(CONFIG_ARCH_TEGRA) += tegra
machine-$(CONFIG_ARCH_U300) += u300
machine-$(CONFIG_ARCH_U8500) += ux500
machine-$(CONFIG_ARCH_VERSATILE) += versatile
machine-$(CONFIG_ARCH_VEXPRESS) += vexpress
machine-$(CONFIG_ARCH_VT8500) += vt8500
machine-$(CONFIG_ARCH_ZX) += zx
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_PLAT_SPEAR) += spear

39
arch/arm/boot/dts/Makefile
View File

@ -74,10 +74,6 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
at91-sama5d4_xplained.dtb \
at91-sama5d4ek.dtb \
at91-vinco.dtb
dtb-$(CONFIG_ARCH_ATLAS6) += \
atlas6-evb.dtb
dtb-$(CONFIG_ARCH_ATLAS7) += \
atlas7-evb.dtb
dtb-$(CONFIG_ARCH_AXXIA) += \
axm5516-amarillo.dtb
dtb-$(CONFIG_ARCH_BCM2835) += \
@ -177,8 +173,6 @@ dtb-$(CONFIG_ARCH_DAVINCI) += \
da850-lego-ev3.dtb
dtb-$(CONFIG_ARCH_DIGICOLOR) += \
cx92755_equinox.dtb
dtb-$(CONFIG_ARCH_EFM32) += \
efm32gg-dk3750.dtb
dtb-$(CONFIG_ARCH_EXYNOS3) += \
exynos3250-artik5-eval.dtb \
exynos3250-monk.dtb \
@ -465,6 +459,9 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-pico-hobbit.dtb \
imx6dl-pico-nymph.dtb \
imx6dl-pico-pi.dtb \
imx6dl-plybas.dtb \
imx6dl-plym2m.dtb \
imx6dl-prtmvt.dtb \
imx6dl-prtrvt.dtb \
imx6dl-prtvt7.dtb \
imx6dl-rex-basic.dtb \
@ -487,6 +484,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-tx6u-811x.dtb \
imx6dl-tx6u-81xx-mb7.dtb \
imx6dl-udoo.dtb \
imx6dl-victgo.dtb \
imx6dl-vicut1.dtb \
imx6dl-wandboard.dtb \
imx6dl-wandboard-revb1.dtb \
imx6dl-wandboard-revd1.dtb \
@ -580,6 +579,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-udoo.dtb \
imx6q-utilite-pro.dtb \
imx6q-var-dt6customboard.dtb \
imx6q-vicut1.dtb \
imx6q-wandboard.dtb \
imx6q-wandboard-revb1.dtb \
imx6q-wandboard-revd1.dtb \
@ -594,6 +594,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6qp-tx6qp-8037-mb7.dtb \
imx6qp-tx6qp-8137.dtb \
imx6qp-tx6qp-8137-mb7.dtb \
imx6qp-vicutp.dtb \
imx6qp-wandboard-revd1.dtb \
imx6qp-zii-rdu2.dtb
dtb-$(CONFIG_SOC_IMX6SL) += \
@ -631,6 +632,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-pico-pi.dtb \
imx6ul-phytec-segin-ff-rdk-emmc.dtb \
imx6ul-phytec-segin-ff-rdk-nand.dtb \
imx6ul-prti6g.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
@ -817,6 +819,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
am335x-lxm.dtb \
am335x-moxa-uc-2101.dtb \
am335x-moxa-uc-8100-me-t.dtb \
am335x-myirtech-myd.dtb \
am335x-nano.dtb \
am335x-netcan-plus-1xx.dtb \
am335x-netcom-plus-2xx.dtb \
@ -888,11 +891,6 @@ dtb-$(CONFIG_ARCH_ACTIONS) += \
owl-s500-labrador-base-m.dtb \
owl-s500-roseapplepi.dtb \
owl-s500-sparky.dtb
dtb-$(CONFIG_ARCH_PICOXCELL) += \
picoxcell-pc7302-pc3x2.dtb \
picoxcell-pc7302-pc3x3.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += \
prima2-evb.dtb
dtb-$(CONFIG_ARCH_PXA) += \
pxa300-raumfeld-connector.dtb \
pxa300-raumfeld-controller.dtb \
@ -912,6 +910,9 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8074-dragonboard.dtb \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
qcom-ipq4018-ap120c-ac.dtb \
qcom-ipq4018-ap120c-ac-bit.dtb \
qcom-ipq4018-jalapeno.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
@ -927,7 +928,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-msm8974-sony-xperia-amami.dtb \
qcom-msm8974-sony-xperia-castor.dtb \
qcom-msm8974-sony-xperia-honami.dtb \
qcom-mdm9615-wp8548-mangoh-green.dtb
qcom-mdm9615-wp8548-mangoh-green.dtb \
qcom-sdx55-mtp.dtb
dtb-$(CONFIG_ARCH_RDA) += \
rda8810pl-orangepi-2g-iot.dtb \
rda8810pl-orangepi-i96.dtb
@ -1224,6 +1226,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-s3-lichee-zero-plus.dtb \
sun8i-s3-pinecube.dtb \
sun8i-t3-cqa3t-bv3.dtb \
sun8i-v3-sl631-imx179.dtb \
sun8i-v3s-licheepi-zero.dtb \
sun8i-v3s-licheepi-zero-dock.dtb \
sun8i-v40-bananapi-m2-berry.dtb
@ -1232,8 +1235,6 @@ dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-cubieboard4.dtb
dtb-$(CONFIG_MACH_SUNIV) += \
suniv-f1c100s-licheepi-nano.dtb
dtb-$(CONFIG_ARCH_TANGO) += \
tango4-vantage-1172.dtb
dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
tegra20-acer-a500-picasso.dtb \
tegra20-harmony.dtb \
@ -1268,8 +1269,6 @@ dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \
tegra124-nyan-big.dtb \
tegra124-nyan-blaze.dtb \
tegra124-venice2.dtb
dtb-$(CONFIG_ARCH_U300) += \
ste-u300.dtb
dtb-$(CONFIG_ARCH_U8500) += \
ste-snowball.dtb \
ste-hrefprev60-stuib.dtb \
@ -1278,6 +1277,7 @@ dtb-$(CONFIG_ARCH_U8500) += \
ste-hrefv60plus-tvk.dtb \
ste-href520-tvk.dtb \
ste-ux500-samsung-golden.dtb \
ste-ux500-samsung-janice.dtb \
ste-ux500-samsung-skomer.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ld4-ref.dtb \
@ -1307,6 +1307,7 @@ dtb-$(CONFIG_ARCH_VT8500) += \
wm8850-w70v2.dtb
dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-cc108.dtb \
zynq-ebaz4205.dtb \
zynq-microzed.dtb \
zynq-parallella.dtb \
zynq-zc702.dtb \
@ -1398,11 +1399,11 @@ dtb-$(CONFIG_ARCH_MSTARV7) += \
mstar-infinity2m-ssd202d-ssd201htv2.dtb \
mstar-infinity3-msc313e-breadbee.dtb \
mstar-mercury5-ssc8336n-midrived08.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
aspeed-ast2600-evb.dtb \
aspeed-bmc-amd-ethanolx.dtb \
aspeed-bmc-ampere-mtjade.dtb \
aspeed-bmc-arm-centriq2400-rep.dtb \
aspeed-bmc-arm-stardragon4800-rep2.dtb \
aspeed-bmc-bytedance-g220a.dtb \
@ -1415,6 +1416,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-facebook-wedge400.dtb \
aspeed-bmc-facebook-yamp.dtb \
aspeed-bmc-facebook-yosemitev2.dtb \
aspeed-bmc-ibm-everest.dtb \
aspeed-bmc-ibm-rainier.dtb \
aspeed-bmc-ibm-rainier-4u.dtb \
aspeed-bmc-intel-s2600wf.dtb \
@ -1434,4 +1436,5 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-opp-witherspoon.dtb \
aspeed-bmc-opp-zaius.dtb \
aspeed-bmc-portwell-neptune.dtb \
aspeed-bmc-quanta-q71l.dtb
aspeed-bmc-quanta-q71l.dtb \
aspeed-bmc-supermicro-x11spi.dtb

13
arch/arm/boot/dts/am335x-evm.dts
View File

@ -684,28 +684,31 @@ vmmc_reg: regulator@12 {
};
};
&mac {
&mac_sw {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
slaves = <1>;
};
&davinci_mdio {
&davinci_mdio_sw {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
&cpsw_emac0 {
&cpsw_port1 {
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
ti,dual-emac-pvid = <1>;
};
&cpsw_port2 {
status = "disabled";
};
&tscadc {

14
arch/arm/boot/dts/am335x-evmsk.dts
View File

@ -596,19 +596,17 @@ vmmc_reg: regulator@12 {
};
};
&mac {
&mac_sw {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
dual_emac = <1>;
status = "okay";
};
&davinci_mdio {
&davinci_mdio_sw {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
@ -619,16 +617,16 @@ ethphy1: ethernet-phy@1 {
};
};
&cpsw_emac0 {
&cpsw_port1 {
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <1>;
ti,dual-emac-pvid = <1>;
};
&cpsw_emac1 {
&cpsw_port2 {
phy-handle = <&ethphy1>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <2>;
ti,dual-emac-pvid = <2>;
};
&mmc1 {

14
arch/arm/boot/dts/am335x-icev2.dts
View File

@ -474,31 +474,29 @@ p10 {
};
};
&cpsw_emac0 {
&cpsw_port1 {
phy-handle = <&ethphy0>;
phy-mode = "rmii";
dual_emac_res_vlan = <1>;
ti,dual-emac-pvid = <1>;
};
&cpsw_emac1 {
&cpsw_port2 {
phy-handle = <&ethphy1>;
phy-mode = "rmii";
dual_emac_res_vlan = <2>;
ti,dual-emac-pvid = <2>;
};
&mac {
&mac_sw {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
dual_emac;
};
&davinci_mdio {
&davinci_mdio_sw {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
reset-delay-us = <2>; /* PHY datasheet states 1uS min */

267
arch/arm/boot/dts/am335x-myirtech-myc.dtsi Normal file
View File

@ -0,0 +1,267 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */
/* Based on code by myc_c335x.dts, MYiRtech.com */
/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */
/dts-v1/;
#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
/ {
model = "MYIR MYC-AM335X";
compatible = "myir,myc-am335x", "ti,am33xx";
cpus {
cpu@0 {
cpu0-supply = <&vdd_core>;
voltage-tolerance = <2>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
vdd_mod: vdd_mod_reg {
compatible = "regulator-fixed";
regulator-name = "vdd-mod";
regulator-always-on;
regulator-boot-on;
};
vdd_core: vdd_core_reg {
compatible = "regulator-fixed";
regulator-name = "vdd-core";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vdd_mod>;
};
leds: leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_mod_pins>;
led_mod: led_mod {
label = "module:user";
gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
panic-indicator;
};
};
};
&cpsw_emac0 {
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mdio_pins_default>;
pinctrl-1 = <&mdio_pins_sleep>;
status = "okay";
phy0: ethernet-phy@4 {
reg = <4>;
};
};
&elm {
status = "okay";
};
&gpmc {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&nand_pins_default>;
pinctrl-1 = <&nand_pins_sleep>;
ranges = <0 0 0x8000000 0x1000000>;
status = "okay";
nand0: nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>;
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE_NONE>;
nand-bus-width = <8>;
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
ti,elm-id = <&elm>;
ti,nand-ecc-opt = "bch8";
#address-cells = <1>;
#size-cells = <1>;
};
};
&i2c0 {
pinctrl-names = "default", "gpio", "sleep";
pinctrl-0 = <&i2c0_pins_default>;
pinctrl-1 = <&i2c0_pins_gpio>;
pinctrl-2 = <&i2c0_pins_sleep>;
clock-frequency = <400000>;
scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
eeprom: eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
vcc-supply = <&vdd_mod>;
};
};
&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&eth_slave1_pins_default>;
pinctrl-1 = <&eth_slave1_pins_sleep>;
slaves = <1>;
status = "okay";
};
&rtc {
system-power-controller;
};
&am33xx_pinmux {
mdio_pins_default: pinmux_mdio_pins_default {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data */
AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk */
>;
};
mdio_pins_sleep: pinmux_mdio_pins_sleep {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
>;
};
eth_slave1_pins_default: pinmux_eth_slave1_pins_default {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_tctl */
AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rctl */
AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td3 */
AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td2 */
AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td1 */
AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td0 */
AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_tclk */
AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rclk */
AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd3 */
AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd2 */
AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd1 */
AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd0 */
>;
};
eth_slave1_pins_sleep: pinmux_eth_slave1_pins_sleep {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
>;
};
i2c0_pins_default: pinmux_i2c0_pins_default {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0) /* I2C0_SDA */
AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0) /* I2C0_SCL */
>;
};
i2c0_pins_gpio: pinmux_i2c0_pins_gpio {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE7) /* gpio3[5] */
AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE7) /* gpio3[6] */
>;
};
i2c0_pins_sleep: pinmux_i2c0_pins_sleep {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE7)
>;
};
led_mod_pins: pinmux_led_mod_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpio3[18] */
>;
};
nand_pins_default: pinmux_nand_pins_default {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad2 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad3 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad4 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad5 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7 */
AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0 */
AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpio0[31] */
AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0 */
AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale */
AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren */
AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) /* gpmc_wen */
AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) /* gpmc_be0n_cle */
>;
};
nand_pins_sleep: pinmux_nand_pins_sleep {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7)
>;
};
};

536
arch/arm/boot/dts/am335x-myirtech-myd.dts Normal file
View File

@ -0,0 +1,536 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */
/* Based on code by myd_c335x.dts, MYiRtech.com */
/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */
/dts-v1/;
#include "am335x-myirtech-myc.dtsi"
#include <dt-bindings/display/tda998x.h>
#include <dt-bindings/input/input.h>
/ {
model = "MYIR MYD-AM335X";
compatible = "myir,myd-am335x", "myir,myc-am335x", "ti,am33xx";
chosen {
stdout-path = &uart0;
};
clk12m: clk12m {
compatible = "fixed-clock";
clock-frequency = <12000000>;
#clock-cells = <0>;
};
gpio_buttons: gpio_buttons {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_buttons_pins>;
#address-cells = <1>;
#size-cells = <0>;
button1: button@0 {
reg = <0>;
label = "button1";
linux,code = <BTN_1>;
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
};
button2: button@1 {
reg = <1>;
label = "button2";
linux,code = <BTN_2>;
gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
};
};
sound: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&master_codec>;
simple-audio-card,frame-master = <&master_codec>;
simple-audio-card,cpu {
sound-dai = <&mcasp0>;
};
master_codec: simple-audio-card,codec@1 {
sound-dai = <&sgtl5000>;
};
simple-audio-card,codec@2 {
sound-dai = <&tda9988>;
};
};
vdd_5v0: vdd_5v0_reg {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
vdd_3v3: vdd_3v3_reg {
compatible = "regulator-fixed";
regulator-name = "vdd-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vdd_5v0>;
};
};
&cpsw_emac1 {
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
};
&davinci_mdio {
phy1: ethernet-phy@6 {
reg = <6>;
eee-broken-1000t;
};
};
&dcan0 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dcan0_pins_default>;
pinctrl-1 = <&dcan0_pins_sleep>;
status = "okay";
};
&dcan1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dcan1_pins_default>;
pinctrl-1 = <&dcan1_pins_sleep>;
status = "okay";
};
&ehrpwm0 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&ehrpwm0_pins_default>;
pinctrl-1 = <&ehrpwm0_pins_sleep>;
status = "okay";
};
&epwmss0 {
status = "okay";
};
&i2c1 {
pinctrl-names = "default", "gpio", "sleep";
pinctrl-0 = <&i2c1_pins_default>;
pinctrl-1 = <&i2c1_pins_gpio>;
pinctrl-2 = <&i2c1_pins_sleep>;
clock-frequency = <400000>;
scl-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio0 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
sgtl5000: sgtl5000@a {
compatible = "fsl,sgtl5000";
reg =<0xa>;
clocks = <&clk12m>;
micbias-resistor-k-ohms = <4>;
micbias-voltage-m-volts = <2250>;
VDDA-supply = <&vdd_3v3>;
VDDIO-supply = <&vdd_3v3>;
#sound-dai-cells = <0>;
};
tda9988: tda9988@70 {
compatible = "nxp,tda998x";
reg =<0x70>;
audio-ports = <TDA998x_I2S 1>;
#sound-dai-cells = <0>;
ports {
port@0 {
hdmi_0: endpoint@0 {
remote-endpoint = <&lcdc_0>;
};
};
};
};
};
&lcdc {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&lcdc_pins_default>;
pinctrl-1 = <&lcdc_pins_sleep>;
blue-and-red-wiring = "straight";
status = "okay";
port {
lcdc_0: endpoint@0 {
remote-endpoint = <&hdmi_0>;
};
};
};
&leds {
pinctrl-0 = <&led_mod_pins &leds_pins>;
led1: led1 {
label = "base:user1";
gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
};
led2: led2 {
label = "base:user2";
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
};
};
&mac {
pinctrl-0 = <&eth_slave1_pins_default>, <&eth_slave2_pins_default>;
pinctrl-1 = <&eth_slave1_pins_sleep>, <&eth_slave2_pins_sleep>;
slaves = <2>;
};
&mcasp0 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp0_pins_default>;
pinctrl-1 = <&mcasp0_pins_sleep>;
op-mode = <0>;
tdm-slots = <2>;
serial-dir = <0 1 2 0>;
tx-num-evt = <32>;
rx-num-evt = <32>;
status = "okay";
#sound-dai-cells = <0>;
};
&mmc1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_sleep>;
cd-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&vdd_3v3>;
status = "okay";
};
&nand0 {
partition@0 {
label = "MLO";
reg = <0x00000 0x20000>;
};
partition@20000 {
label = "boot";
reg = <0x20000 0x80000>;
};
};
&tscadc {
status = "okay";
adc: adc {
ti,adc-channels = <0 1 2 3 4 5 6>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart1_pins_default>;
pinctrl-1 = <&uart1_pins_sleep>;
linux,rs485-enabled-at-boot-time;
status = "okay";
};
&uart2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart2_pins_default>;
pinctrl-1 = <&uart2_pins_sleep>;
status = "okay";
};
&usb {
pinctrl-names = "default";
pinctrl-0 = <&usb_pins>;
};
&usb0 {
dr_mode = "otg";
};
&usb0_phy {
vcc-supply = <&vdd_5v0>;
};
&usb1 {
dr_mode = "host";
};
&usb1_phy {
vcc-supply = <&vdd_5v0>;
};
&vdd_mod {
vin-supply = <&vdd_3v3>;
};
&am33xx_pinmux {
dcan0_pins_default: pinmux_dcan0_pins_default {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* dcan0_tx_mux2 */
AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT, MUX_MODE2) /* dcan0_rx_mux2 */
>;
};
dcan0_pins_sleep: pinmux_dcan0_pins_sleep {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE7)
>;
};
dcan1_pins_default: pinmux_dcan1_pins_default {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* dcan1_tx_mux0 */
AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* dcan1_rx_mux0 */
>;
};
dcan1_pins_sleep: pinmux_dcan1_pins_sleep {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE7)
>;
};
ehrpwm0_pins_default: pinmux_ehrpwm0_pins_default {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_OUTPUT, MUX_MODE3) /* ehrpwm0A_mux1 */
>;
};
ehrpwm0_pins_sleep: pinmux_ehrpwm0_pins_sleep {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
>;
};
eth_slave2_pins_default: pinmux_eth_slave2_pins_default {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_tctl */
AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rctl */
AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td3 */
AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td2 */
AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td1 */
AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td0 */
AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_tclk */
AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rclk */
AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rd3 */
AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rd2 */
AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2 /* rgmii2_rd1 */)
AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2 /* rgmii2_rd0 */)
>;
};
eth_slave2_pins_sleep: pinmux_eth_slave2_pins_sleep {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
>;
};
gpio_buttons_pins: pinmux_gpio_buttons_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpio3[0] */
AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT, MUX_MODE7) /* gpio0[29] */
>;
};
i2c1_pins_default: pinmux_i2c1_pins_default {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE2) /* I2C1_SDA_mux3 */
AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE2) /* I2C1_SCL_mux3 */
>;
};
i2c1_pins_gpio: pinmux_i2c1_pins_gpio {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE7) /* gpio0[4] */
AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE7) /* gpio0[5] */
>;
};
i2c1_pins_sleep: pinmux_i2c1_pins_sleep {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLDOWN, MUX_MODE7)
>;
};
lcdc_pins_default: pinmux_lcdc_pins_default {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) /* lcd_data0 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) /* lcd_data1 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) /* lcd_data2 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) /* lcd_data3 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) /* lcd_data4 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) /* lcd_data5 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) /* lcd_data6 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) /* lcd_data7 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) /* lcd_data8 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) /* lcd_data9 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) /* lcd_data10 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) /* lcd_data11 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) /* lcd_data12 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) /* lcd_data13 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) /* lcd_data14 */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) /* lcd_data15 */
AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) /* lcd_vsync */
AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) /* lcd_hsync */
AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) /* lcd_pclk */
AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) /* lcd_ac_bias_en */
>;
};
lcdc_pins_sleep: pinmux_lcdc_pins_sleep {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
>;
};
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* gpio0[27] */
AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE7) /* gpio0[3] */
>;
};
mcasp0_pins_default: pinmux_mcasp0_pins_default {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_aclkx_mux0 */
AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_fsx_mux0 */
AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mcasp0_axr2_mux0 */
AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_axr1_mux0 */
>;
};
mcasp0_pins_sleep: pinmux_mcasp0_pins_sleep {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7)
>;
};
mmc1_pins_default: pinmux_mmc1_pins_default {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat3 */
AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat2 */
AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat1 */
AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat0 */
AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_clk */
AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_cmd */
AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* gpio3[21] */
>;
};
mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLDOWN, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLDOWN, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLDOWN, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLDOWN, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLDOWN, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7)
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) /* uart0_rxd */
AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* uart0_txd */
>;
};
uart1_pins_default: pinmux_uart1_pins_default {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) /* uart1_rxd */
AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* uart1_txd */
>;
};
uart1_pins_sleep: pinmux_uart1_pins_sleep {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLDOWN, MUX_MODE7)
>;
};
uart2_pins_default: pinmux_uart2_pins_default {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE6) /* uart2_rxd_mux1 */
AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_OUTPUT, MUX_MODE6) /* uart2_txd_mux1 */
>;
};
uart2_pins_sleep: pinmux_uart2_pins_sleep {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
>;
};
usb_pins: pinmux_usb_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_USB0_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* USB0_DRVVBUS */
AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* USB1_DRVVBUS */
>;
};
};

49
arch/arm/boot/dts/am33xx-l4.dtsi
View File

@ -765,6 +765,55 @@ cpsw_emac1: slave@300 {
phys = <&phy_gmii_sel 2 1>;
};
};
mac_sw: switch@0 {
compatible = "ti,am335x-cpsw-switch", "ti,cpsw-switch";
reg = <0x0 0x4000>;
ranges = <0 0 0x4000>;
clocks = <&cpsw_125mhz_gclk>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
syscon = <&scm_conf>;
status = "disabled";
interrupts = <40 41 42 43>;
interrupt-names = "rx_thresh", "rx", "tx", "misc";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
cpsw_port1: port@1 {
reg = <1>;
label = "port1";
mac-address = [ 00 00 00 00 00 00 ];
phys = <&phy_gmii_sel 1 1>;
};
cpsw_port2: port@2 {
reg = <2>;
label = "port2";
mac-address = [ 00 00 00 00 00 00 ];
phys = <&phy_gmii_sel 2 1>;
};
};
davinci_mdio_sw: mdio@1000 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
clocks = <&cpsw_125mhz_gclk>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
reg = <0x1000 0x100>;
};
cpts {
clocks = <&cpsw_cpts_rft_clk>;
clock-names = "cpts";
};
};
};
target-module@180000 { /* 0x4a180000, ap 5 10.0 */

4
arch/arm/boot/dts/am574x-idk.dts
View File

@ -39,3 +39,7 @@ &mmc2 {
&m_can0 {
status = "disabled";
};
&emif1 {
status = "okay";
};

2
arch/arm/boot/dts/armada-385-linksys.dtsi
View File

@ -148,6 +148,8 @@ nand: nand@0 {
reg = <0>;
label = "pxa3xx_nand-0";
nand-rb = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
marvell,nand-keep-config;
nand-on-flash-bbt;
};

28
arch/arm/boot/dts/armada-388-helios4.dts
View File

@ -70,6 +70,9 @@ reg_5p0v_usb: regulator-5v-usb {
system-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&helios_system_led_pins>;
status-led {
label = "helios4:green:status";
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
@ -86,6 +89,9 @@ fault-led {
io-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&helios_io_led_pins>;
sata1-led {
label = "helios4:green:ata1";
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
@ -121,11 +127,15 @@ usb-led {
fan1: j10-pwm {
compatible = "pwm-fan";
pwms = <&gpio1 9 40000>; /* Target freq:25 kHz */
pinctrl-names = "default";
pinctrl-0 = <&helios_fan1_pins>;
};
fan2: j17-pwm {
compatible = "pwm-fan";
pwms = <&gpio1 23 40000>; /* Target freq:25 kHz */
pinctrl-names = "default";
pinctrl-0 = <&helios_fan2_pins>;
};
usb2_phy: usb2-phy {
@ -286,16 +296,22 @@ helios_sdhci_pins: helios-sdhci-pins {
"mpp39", "mpp40";
marvell,function = "sd0";
};
helios_led_pins: helios-led-pins {
marvell,pins = "mpp24", "mpp25",
"mpp49", "mpp50",
helios_system_led_pins: helios-system-led-pins {
marvell,pins = "mpp24", "mpp25";
marvell,function = "gpio";
};
helios_io_led_pins: helios-io-led-pins {
marvell,pins = "mpp49", "mpp50",
"mpp52", "mpp53",
"mpp54";
marvell,function = "gpio";
};
helios_fan_pins: helios-fan-pins {
marvell,pins = "mpp41", "mpp43",
"mpp48", "mpp55";
helios_fan1_pins: helios_fan1_pins {
marvell,pins = "mpp41", "mpp43";
marvell,function = "gpio";
};
helios_fan2_pins: helios_fan2_pins {
marvell,pins = "mpp48", "mpp55";
marvell,function = "gpio";
};
microsom_spi1_cs_pins: spi1-cs-pins {

8
arch/arm/boot/dts/aspeed-ast2600-evb.dts
View File

@ -237,3 +237,11 @@ &i2c15 {
&fsim0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&uhci {
status = "okay";
};

2
arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts
View File

@ -218,7 +218,7 @@ &kcs4 {
&lpc_snoop {
status = "okay";
snoop-ports = <0x80>;
snoop-ports = <0x80>, <0x81>;
};
&lpc_ctrl {

558
arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts Normal file
View File

@ -0,0 +1,558 @@
// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "Ampere Mt. Jade BMC";
compatible = "ampere,mtjade-bmc", "aspeed,ast2500";
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
vga_memory: framebuffer@9f000000 {
no-map;
reg = <0x9f000000 0x01000000>; /* 16M */
};
gfx_memory: framebuffer {
size = <0x01000000>;
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
video_engine_memory: jpegbuffer {
size = <0x02000000>; /* 32M */
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
};
leds {
compatible = "gpio-leds";
fault {
gpios = <&gpio ASPEED_GPIO(B, 6) GPIO_ACTIVE_HIGH>;
};
identify {
gpios = <&gpio ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>;
};
};
gpio-keys {
compatible = "gpio-keys";
shutdown_ack {
label = "SHUTDOWN_ACK";
gpios = <&gpio ASPEED_GPIO(G, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(G, 2)>;
};
reboot_ack {
label = "REBOOT_ACK";
gpios = <&gpio ASPEED_GPIO(J, 3) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(J, 3)>;
};
S0_overtemp {
label = "S0_OVERTEMP";
gpios = <&gpio ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(G, 3)>;
};
S0_hightemp {
label = "S0_HIGHTEMP";
gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(J, 0)>;
};
S0_cpu_fault {
label = "S0_CPU_FAULT";
gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>;
linux,code = <ASPEED_GPIO(J, 1)>;
};
S1_overtemp {
label = "S1_OVERTEMP";
gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(Z, 6)>;
};
S1_hightemp {
label = "S1_HIGHTEMP";
gpios = <&gpio ASPEED_GPIO(AB, 0) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(AB, 0)>;
};
S1_cpu_fault {
label = "S1_CPU_FAULT";
gpios = <&gpio ASPEED_GPIO(Z, 1) GPIO_ACTIVE_HIGH>;
linux,code = <ASPEED_GPIO(Z, 1)>;
};
id_button {
label = "ID_BUTTON";
gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(Q, 5)>;
};
};
gpioA0mux: mux-controller {
compatible = "gpio-mux";
#mux-control-cells = <0>;
mux-gpios = <&gpio ASPEED_GPIO(A, 0) GPIO_ACTIVE_LOW>;
};
adc0mux: adc0mux {
compatible = "io-channel-mux";
io-channels = <&adc 0>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioA0mux>;
channels = "s0", "s1";
};
adc1mux: adc1mux {
compatible = "io-channel-mux";
io-channels = <&adc 1>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioA0mux>;
channels = "s0", "s1";
};
adc2mux: adc2mux {
compatible = "io-channel-mux";
io-channels = <&adc 2>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioA0mux>;
channels = "s0", "s1";
};
adc3mux: adc3mux {
compatible = "io-channel-mux";
io-channels = <&adc 3>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioA0mux>;
channels = "s0", "s1";
};
adc4mux: adc4mux {
compatible = "io-channel-mux";
io-channels = <&adc 4>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioA0mux>;
channels = "s0", "s1";
};
adc5mux: adc5mux {
compatible = "io-channel-mux";
io-channels = <&adc 5>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioA0mux>;
channels = "s0", "s1";
};
adc6mux: adc6mux {
compatible = "io-channel-mux";
io-channels = <&adc 6>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioA0mux>;
channels = "s0", "s1";
};
adc7mux: adc7mux {
compatible = "io-channel-mux";
io-channels = <&adc 7>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioA0mux>;
channels = "s0", "s1";
};
adc8mux: adc8mux {
compatible = "io-channel-mux";
io-channels = <&adc 8>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioA0mux>;
channels = "s0", "s1";
};
adc9mux: adc9mux {
compatible = "io-channel-mux";
io-channels = <&adc 9>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioA0mux>;
channels = "s0", "s1";
};
adc10mux: adc10mux {
compatible = "io-channel-mux";
io-channels = <&adc 10>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioA0mux>;
channels = "s0", "s1";
};
adc11mux: adc11mux {
compatible = "io-channel-mux";
io-channels = <&adc 11>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioA0mux>;
channels = "s0", "s1";
};
adc12mux: adc12mux {
compatible = "io-channel-mux";
io-channels = <&adc 12>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioA0mux>;
channels = "s0", "s1";
};
adc13mux: adc13mux {
compatible = "io-channel-mux";
io-channels = <&adc 13>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioA0mux>;
channels = "s0", "s1";
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc0mux 0>, <&adc0mux 1>,
<&adc1mux 0>, <&adc1mux 1>,
<&adc2mux 0>, <&adc2mux 1>,
<&adc3mux 0>, <&adc3mux 1>,
<&adc4mux 0>, <&adc4mux 1>,
<&adc5mux 0>, <&adc5mux 1>,
<&adc6mux 0>, <&adc6mux 1>,
<&adc7mux 0>, <&adc7mux 1>,
<&adc8mux 0>, <&adc8mux 1>,
<&adc9mux 0>, <&adc9mux 1>,
<&adc10mux 0>, <&adc10mux 1>,
<&adc11mux 0>, <&adc11mux 1>,
<&adc12mux 0>, <&adc12mux 1>,
<&adc13mux 0>, <&adc13mux 1>;
};
iio-hwmon-adc14 {
compatible = "iio-hwmon";
io-channels = <&adc 14>;
};
iio-hwmon-battery {
compatible = "iio-hwmon";
io-channels = <&adc 15>;
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
/* spi-max-frequency = <50000000>; */
#include "openbmc-flash-layout.dtsi"
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
m25p,fast-read;
label = "pnor";
/* spi-max-frequency = <100000000>; */
};
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default
&pinctrl_ncts1_default
&pinctrl_nrts1_default>;
};
&uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd2_default
&pinctrl_rxd2_default>;
};
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd3_default
&pinctrl_rxd3_default>;
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd4_default
&pinctrl_rxd4_default>;
};
/* The BMC's uart */
&uart5 {
status = "okay";
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
eeprom@50 {
compatible = "microchip,24c64", "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
inlet_mem2: tmp175@28 {
compatible = "ti,tmp175";
reg = <0x28>;
};
inlet_cpu: tmp175@29 {
compatible = "ti,tmp175";
reg = <0x29>;
};
inlet_mem1: tmp175@2a {
compatible = "ti,tmp175";
reg = <0x2a>;
};
outlet_cpu: tmp175@2b {
compatible = "ti,tmp175";
reg = <0x2b>;
};
outlet1: tmp175@2c {
compatible = "ti,tmp175";
reg = <0x2c>;
};
outlet2: tmp175@2d {
compatible = "ti,tmp175";
reg = <0x2d>;
};
};
&i2c4 {
status = "okay";
rtc@51 {
compatible = "nxp,pcf85063a";
reg = <0x51>;
};
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
psu@58 {
compatible = "pmbus";
reg = <0x58>;
};
psu@59 {
compatible = "pmbus";
reg = <0x59>;
};
};
&i2c7 {
status = "okay";
};
&i2c8 {
status = "okay";
};
&i2c9 {
status = "okay";
};
&gfx {
status = "okay";
memory-region = <&gfx_memory>;
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2_default &pinctrl_pwm3_default
&pinctrl_pwm4_default &pinctrl_pwm5_default
&pinctrl_pwm6_default &pinctrl_pwm7_default>;
fan@0 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x04>;
};
fan@1 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x05>;
};
fan@2 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x06>;
};
fan@3 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x07>;
};
fan@4 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x08>;
};
fan@5 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x09>;
};
fan@6 {
reg = <0x05>;
aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
};
fan@7 {
reg = <0x05>;
aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
};
fan@8 {
reg = <0x06>;
aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
};
fan@9 {
reg = <0x06>;
aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
};
fan@10 {
reg = <0x07>;
aspeed,fan-tach-ch = /bits/ 8 <0x0e>;
};
fan@11 {
reg = <0x07>;
aspeed,fan-tach-ch = /bits/ 8 <0x0f>;
};
};
&vhub {
status = "okay";
};
&adc {
status = "okay";
};
&video {
status = "okay";
memory-region = <&video_engine_memory>;
};
&gpio {
gpio-line-names =
/*A0-A7*/ "","","","S0_BMC_SPECIAL_BOOT","","","","",
/*B0-B7*/ "BMC_SELECT_EEPROM","","","",
"POWER_BUTTON","","","",
/*C0-C7*/ "","","","","","","","",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "","","","","","","","",
/*F0-F7*/ "","","BMC_SYS_PSON_L","S0_DDR_SAVE","PGOOD",
"S1_DDR_SAVE","","",
/*G0-G7*/ "S0_FW_BOOT_OK","SHD_REQ_L","","S0_OVERTEMP_L","","",
"","",
/*H0-H7*/ "","","","","","","","",
/*I0-I7*/ "","","S1_BMC_SPECIAL_BOOT","","","","","",
/*J0-J7*/ "S0_HIGHTEMP_L","S0_FAULT_L","S0_SCP_AUTH_FAIL_L","",
"","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","BMC_SYSRESET_L","SPI_AUTH_FAIL_L","","","",
/*M0-M7*/ "","","","","","","","",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "","","","","","","","",
/*Q0-Q7*/ "","","","","","UID_BUTTON","","",
/*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","","","RESET_BUTTON","","",
/*S0-S7*/ "","","","","","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","","","","",
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","","","","","","",
/*Y0-Y7*/ "","","","","","","","",
/*Z0-Z7*/ "S0_BMC_PLIMIT","S1_FAULT_L","S1_FW_BOOT_OK","","",
"S1_SCP_AUTH_FAIL_L","S1_OVERTEMP_L","",
/*AA0-AA7*/ "","","","","","","","",
/*AB0-AB7*/ "S1_HIGHTEMP_L","S1_BMC_PLIMIT","S0_BMC_DDR_ADDR",
"S1_BMC_DDR_ADR","","","","",
/*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L",
"BMC_OCP_PG";
};

10
arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts
View File

@ -446,7 +446,11 @@ channel_3_3: i2c@3 {
&i2c4 {
status = "okay";
ipmb0@10 {
compatible = "ipmb-dev";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
i2c-protocol;
};
};
&i2c5 {
@ -901,14 +905,14 @@ fan@5 {
&gpio {
pin_gpio_i3 {
gpio-hog;
gpios = <ASPEED_GPIO(I, 3) GPIO_ACTIVE_LOW>;
gpios = <ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "NCSI_BMC_R_SEL";
};
pin_gpio_b6 {
gpio-hog;
gpios = <ASPEED_GPIO(B, 6) GPIO_ACTIVE_LOW>;
gpios = <ASPEED_GPIO(B, 6) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "EN_NCSI_SWITCH_N";
};

775
arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts Normal file
View File

@ -0,0 +1,775 @@
// SPDX-License-Identifier: GPL-2.0-or-later
// Copyright 2020 IBM Corp.
/dts-v1/;
#include "aspeed-g6.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/leds/leds-pca955x.h>
/ {
model = "Everest";
compatible = "ibm,everest-bmc", "aspeed,ast2600";
aliases {
i2c100 = &cfam0_i2c0;
i2c101 = &cfam0_i2c1;
i2c110 = &cfam0_i2c10;
i2c111 = &cfam0_i2c11;
i2c112 = &cfam0_i2c12;
i2c113 = &cfam0_i2c13;
i2c114 = &cfam0_i2c14;
i2c115 = &cfam0_i2c15;
i2c202 = &cfam1_i2c2;
i2c203 = &cfam1_i2c3;
i2c210 = &cfam1_i2c10;
i2c211 = &cfam1_i2c11;
i2c214 = &cfam1_i2c14;
i2c215 = &cfam1_i2c15;
i2c216 = &cfam1_i2c16;
i2c217 = &cfam1_i2c17;
i2c300 = &cfam2_i2c0;
i2c301 = &cfam2_i2c1;
i2c310 = &cfam2_i2c10;
i2c311 = &cfam2_i2c11;
i2c312 = &cfam2_i2c12;
i2c313 = &cfam2_i2c13;
i2c314 = &cfam2_i2c14;
i2c315 = &cfam2_i2c15;
i2c402 = &cfam3_i2c2;
i2c403 = &cfam3_i2c3;
i2c410 = &cfam3_i2c10;
i2c411 = &cfam3_i2c11;
i2c414 = &cfam3_i2c14;
i2c415 = &cfam3_i2c15;
i2c416 = &cfam3_i2c16;
i2c417 = &cfam3_i2c17;
serial4 = &uart5;
spi10 = &cfam0_spi0;
spi11 = &cfam0_spi1;
spi12 = &cfam0_spi2;
spi13 = &cfam0_spi3;
spi20 = &cfam1_spi0;
spi21 = &cfam1_spi1;
spi22 = &cfam1_spi2;
spi23 = &cfam1_spi3;
spi30 = &cfam2_spi0;
spi31 = &cfam2_spi1;
spi32 = &cfam2_spi2;
spi33 = &cfam2_spi3;
spi40 = &cfam3_spi0;
spi41 = &cfam3_spi1;
spi42 = &cfam3_spi2;
spi43 = &cfam3_spi3;
};
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* LPC FW cycle bridge region requires natural alignment */
flash_memory: region@b8000000 {
no-map;
reg = <0xb8000000 0x04000000>; /* 64M */
};
/* 48MB region from the end of flash to start of vga memory */
ramoops@bc000000 {
compatible = "ramoops";
reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */
record-size = <0x8000>;
console-size = <0x8000>;
pmsg-size = <0x8000>;
max-reason = <3>; /* KMSG_DUMP_EMERG */
};
/* VGA region is dictated by hardware strapping */
vga_memory: region@bf000000 {
no-map;
compatible = "shared-dma-pool";
reg = <0xbf000000 0x01000000>; /* 16M */
};
};
};
&ehci1 {
status = "okay";
};
&emmc_controller {
status = "okay";
};
&pinctrl_emmc_default {
bias-disable;
};
&emmc {
status = "okay";
};
&fsim0 {
status = "okay";
#address-cells = <2>;
#size-cells = <0>;
/*
* CFAM Reset is supposed to be active low but pass1 hardware is wired
* active high.
*/
cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
cfam@0,0 {
reg = <0 0>;
#address-cells = <1>;
#size-cells = <1>;
chip-id = <0>;
scom@1000 {
compatible = "ibm,fsi2pib";
reg = <0x1000 0x400>;
};
i2c@1800 {
compatible = "ibm,fsi-i2c-master";
reg = <0x1800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam0_i2c0: i2c-bus@0 {
reg = <0>; /* OMI01 */
};
cfam0_i2c1: i2c-bus@1 {
reg = <1>; /* OMI23 */
};
cfam0_i2c10: i2c-bus@a {
reg = <10>; /* OP3A */
};
cfam0_i2c11: i2c-bus@b {
reg = <11>; /* OP3B */
};
cfam0_i2c12: i2c-bus@c {
reg = <12>; /* OP4A */
};
cfam0_i2c13: i2c-bus@d {
reg = <13>; /* OP4B */
};
cfam0_i2c14: i2c-bus@e {
reg = <14>; /* OP5A */
};
cfam0_i2c15: i2c-bus@f {
reg = <15>; /* OP5B */
};
};
fsi2spi@1c00 {
compatible = "ibm,fsi2spi";
reg = <0x1c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam0_spi0: spi@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam0_spi1: spi@20 {
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam0_spi2: spi@40 {
reg = <0x40>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam0_spi3: spi@60 {
reg = <0x60>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
};
sbefifo@2400 {
compatible = "ibm,p9-sbefifo";
reg = <0x2400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
fsi_occ0: occ {
compatible = "ibm,p10-occ";
};
};
fsi_hub0: hub@3400 {
compatible = "fsi-master-hub";
reg = <0x3400 0x400>;
#address-cells = <2>;
#size-cells = <0>;
};
};
};
&fsi_hub0 {
cfam@1,0 {
reg = <1 0>;
#address-cells = <1>;
#size-cells = <1>;
chip-id = <1>;
scom@1000 {
compatible = "ibm,fsi2pib";
reg = <0x1000 0x400>;
};
i2c@1800 {
compatible = "ibm,fsi-i2c-master";
reg = <0x1800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam1_i2c2: i2c-bus@2 {
reg = <2>; /* OMI45 */
};
cfam1_i2c3: i2c-bus@3 {
reg = <3>; /* OMI67 */
};
cfam1_i2c10: i2c-bus@a {
reg = <10>; /* OP3A */
};
cfam1_i2c11: i2c-bus@b {
reg = <11>; /* OP3B */
};
cfam1_i2c14: i2c-bus@e {
reg = <14>; /* OP5A */
};
cfam1_i2c15: i2c-bus@f {
reg = <15>; /* OP5B */
};
cfam1_i2c16: i2c-bus@10 {
reg = <16>; /* OP6A */
};
cfam1_i2c17: i2c-bus@11 {
reg = <17>; /* OP6B */
};
};
fsi2spi@1c00 {
compatible = "ibm,fsi2spi";
reg = <0x1c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam1_spi0: spi@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam1_spi1: spi@20 {
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam1_spi2: spi@40 {
reg = <0x40>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam1_spi3: spi@60 {
reg = <0x60>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
};
sbefifo@2400 {
compatible = "ibm,p9-sbefifo";
reg = <0x2400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
fsi_occ1: occ {
compatible = "ibm,p10-occ";
};
};
fsi_hub1: hub@3400 {
compatible = "fsi-master-hub";
reg = <0x3400 0x400>;
#address-cells = <2>;
#size-cells = <0>;
no-scan-on-init;
};
};
cfam@2,0 {
reg = <2 0>;
#address-cells = <1>;
#size-cells = <1>;
chip-id = <2>;
scom@1000 {
compatible = "ibm,fsi2pib";
reg = <0x1000 0x400>;
};
i2c@1800 {
compatible = "ibm,fsi-i2c-master";
reg = <0x1800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam2_i2c0: i2c-bus@0 {
reg = <0>; /* OM01 */
};
cfam2_i2c1: i2c-bus@1 {
reg = <1>; /* OM23 */
};
cfam2_i2c10: i2c-bus@a {
reg = <10>; /* OP3A */
};
cfam2_i2c11: i2c-bus@b {
reg = <11>; /* OP3B */
};
cfam2_i2c12: i2c-bus@c {
reg = <12>; /* OP4A */
};
cfam2_i2c13: i2c-bus@d {
reg = <13>; /* OP4B */
};
cfam2_i2c14: i2c-bus@e {
reg = <14>; /* OP5A */
};
cfam2_i2c15: i2c-bus@f {
reg = <15>; /* OP5B */
};
};
fsi2spi@1c00 {
compatible = "ibm,fsi2spi";
reg = <0x1c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam2_spi0: spi@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam2_spi1: spi@20 {
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam2_spi2: spi@40 {
reg = <0x40>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam2_spi3: spi@60 {
reg = <0x60>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
};
sbefifo@2400 {
compatible = "ibm,p9-sbefifo";
reg = <0x2400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
fsi_occ2: occ {
compatible = "ibm,p10-occ";
};
};
fsi_hub2: hub@3400 {
compatible = "fsi-master-hub";
reg = <0x3400 0x400>;
#address-cells = <2>;
#size-cells = <0>;
no-scan-on-init;
};
};
cfam@3,0 {
reg = <3 0>;
#address-cells = <1>;
#size-cells = <1>;
chip-id = <3>;
scom@1000 {
compatible = "ibm,fsi2pib";
reg = <0x1000 0x400>;
};
i2c@1800 {
compatible = "ibm,fsi-i2c-master";
reg = <0x1800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam3_i2c2: i2c-bus@2 {
reg = <2>; /* OM45 */
};
cfam3_i2c3: i2c-bus@3 {
reg = <3>; /* OM67 */
};
cfam3_i2c10: i2c-bus@a {
reg = <10>; /* OP3A */
};
cfam3_i2c11: i2c-bus@b {
reg = <11>; /* OP3B */
};
cfam3_i2c14: i2c-bus@e {
reg = <14>; /* OP5A */
};
cfam3_i2c15: i2c-bus@f {
reg = <15>; /* OP5B */
};
cfam3_i2c16: i2c-bus@10 {
reg = <16>; /* OP6A */
};
cfam3_i2c17: i2c-bus@11 {
reg = <17>; /* OP6B */
};
};
fsi2spi@1c00 {
compatible = "ibm,fsi2spi";
reg = <0x1c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam3_spi0: spi@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam3_spi1: spi@20 {
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam3_spi2: spi@40 {
reg = <0x40>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam3_spi3: spi@60 {
reg = <0x60>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
};
sbefifo@2400 {
compatible = "ibm,p9-sbefifo";
reg = <0x2400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
fsi_occ3: occ {
compatible = "ibm,p10-occ";
};
};
fsi_hub3: hub@3400 {
compatible = "fsi-master-hub";
reg = <0x3400 0x400>;
#address-cells = <2>;
#size-cells = <0>;
no-scan-on-init;
};
};
};
/* Legacy OCC numbering (to get rid of when userspace is fixed) */
&fsi_occ0 {
reg = <1>;
};
&fsi_occ1 {
reg = <2>;
};
&fsi_occ2 {
reg = <3>;
};
&fsi_occ3 {
reg = <4>;
};
&ibt {
status = "okay";
};
&vuart1 {
status = "okay";
};
&vuart2 {
status = "okay";
};
&lpc_ctrl {
status = "okay";
memory-region = <&flash_memory>;
};
&kcs4 {
compatible = "openbmc,mctp-lpc";
status = "okay";
};
&mac2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii3_default>;
clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>,
<&syscon ASPEED_CLK_MAC3RCLK>;
clock-names = "MACCLK", "RCLK";
use-ncsi;
};
&mac3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii4_default>;
clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>,
<&syscon ASPEED_CLK_MAC4RCLK>;
clock-names = "MACCLK", "RCLK";
use-ncsi;
};
&xdma {
status = "okay";
memory-region = <&vga_memory>;
};

3
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
View File

@ -195,6 +195,7 @@ &pinctrl_emmc_default {
&emmc {
status = "okay";
clk-phase-mmc-hs200 = <180>, <180>;
};
&fsim0 {
@ -579,7 +580,7 @@ tca9554@40 {
gpio-controller;
#gpio-cells = <2>;
smbus0 {
smbus0-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;

37
arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
View File

@ -204,6 +204,39 @@ iio-hwmon {
};
&gpio {
gpio-line-names =
/*A0-A7*/ "","","","","","","","",
/*B0-B7*/ "","","front-psu","checkstop","cfam-reset","","","init-ok",
/*C0-C7*/ "","","","","","","","",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "","","","","","","","",
/*F0-F7*/ "ps0-presence","ps1-presence","","","front-memory","","","",
/*G0-G7*/ "","","","","","","","",
/*H0-H7*/ "","","","","front-fan","","","",
/*I0-I7*/ "front-syshealth","front-syshot","mux-gpios","enable-gpios","","","","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","","","",
/*M0-M7*/ "","","","","","","","",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "","","","","","","","",
/*Q0-Q7*/ "","","","","","","","",
/*R0-R7*/ "","power","trans-gpios","","","","","",
/*S0-S7*/ "","","","","","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","","","","",
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","","","","","","",
/*Y0-Y7*/ "","","","","","","","",
/*Z0-Z7*/ "","","","","","","","identify",
/*AA0-AA7*/ "clock-gpios","","data-gpios","","","","","",
/*AB0-AB7*/ "","","","","","","","",
/*AC0-AC7*/ "","","","","","","","";
};
&fmc {
status = "okay";
@ -756,12 +789,12 @@ &i2c11 {
status = "okay";
power-supply@58 {
compatible = "pmbus";
compatible = "inspur,ipsps1";
reg = <0x58>;
};
power-supply@59 {
compatible = "pmbus";
compatible = "inspur,ipsps1";
reg = <0x59>;
};
};

16
arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts
View File

@ -827,7 +827,7 @@ tca9554@39 {
gpio-controller;
#gpio-cells = <2>;
smbus0 {
smbus0-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
@ -852,7 +852,7 @@ tca9554@39 {
gpio-controller;
#gpio-cells = <2>;
smbus1 {
smbus1-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
@ -900,7 +900,7 @@ tca9554@39 {
gpio-controller;
#gpio-cells = <2>;
smbus2 {
smbus2-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
@ -925,7 +925,7 @@ tca9554@39 {
gpio-controller;
#gpio-cells = <2>;
smbus3 {
smbus3-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
@ -992,7 +992,7 @@ tca9554@39 {
gpio-controller;
#gpio-cells = <2>;
smbus4 {
smbus4-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
@ -1017,7 +1017,7 @@ tca9554@39 {
gpio-controller;
#gpio-cells = <2>;
smbus5 {
smbus5-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
@ -1065,7 +1065,7 @@ tca9554@39 {
gpio-controller;
#gpio-cells = <2>;
smbus6 {
smbus6-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
@ -1090,7 +1090,7 @@ tca9554@39 {
gpio-controller;
#gpio-cells = <2>;
smbus7 {
smbus7-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;

5
arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts
View File

@ -582,6 +582,11 @@ &i2c11 {
/* TMP275A */
/* TMP275A */
rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};
tmp275@48 {
compatible = "ti,tmp275";
reg = <0x48>;

2
arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
View File

@ -121,6 +121,8 @@ &i2c5 {
pca9555@27 {
compatible = "nxp,pca9555";
reg = <0x27>;
gpio-controller;
#gpio-cells = <2>;
};
};

137
arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts Normal file
View File

@ -0,0 +1,137 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2020 Super Micro Computer, Inc
/dts-v1/;
#include "aspeed-g5.dtsi"
/ {
model = "X11SPI BMC";
compatible = "supermicro,x11spi-bmc", "aspeed,ast2500";
chosen {
stdout-path = &uart5;
bootargs = "earlyprintk";
};
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
vga_memory: framebuffer@7f000000 {
no-map;
reg = <0x7f000000 0x01000000>;
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
<&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
<&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>;
};
};
&gpio {
status = "okay";
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
#include "openbmc-flash-layout.dtsi"
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
m25p,fast-read;
label = "pnor";
};
};
&uart5 {
status = "okay";
};
&mac0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
<&syscon ASPEED_CLK_MAC1RCLK>;
clock-names = "MACCLK", "RCLK";
use-ncsi;
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
};
&i2c7 {
status = "okay";
};
&i2c13 {
status = "okay";
};
&gfx {
status = "okay";
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
&pinctrl_pwm2_default &pinctrl_pwm3_default
&pinctrl_pwm4_default &pinctrl_pwm5_default
&pinctrl_pwm6_default &pinctrl_pwm7_default>;
};

1
arch/arm/boot/dts/aspeed-g4.dtsi
View File

@ -375,6 +375,7 @@ lpc_snoop: lpc-snoop@10 {
compatible = "aspeed,ast2400-lpc-snoop";
reg = <0x10 0x8>;
interrupts = <8>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};

1
arch/arm/boot/dts/aspeed-g5.dtsi
View File

@ -497,6 +497,7 @@ lpc_snoop: lpc-snoop@10 {
compatible = "aspeed,ast2500-lpc-snoop";
reg = <0x10 0x8>;
interrupts = <8>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};

1
arch/arm/boot/dts/aspeed-g6.dtsi
View File

@ -524,6 +524,7 @@ lpc_snoop: lpc-snoop@0 {
compatible = "aspeed,ast2600-lpc-snoop";
reg = <0x0 0x80>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};

1
arch/arm/boot/dts/at91-kizbox3_common.dtsi
View File

@ -341,7 +341,6 @@ &shutdown_controller {
input@0 {
reg = <0>;
atmel,wakeup-type = "low";
};
};

1
arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
View File

@ -142,7 +142,6 @@ shdwc@f8048010 {
input@0 {
reg = <0>;
atmel,wakeup-type = "low";
};
};

22
arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
View File

@ -43,14 +43,20 @@ uart6: serial@200 {
&i2c0 {
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-names = "default";
pinctrl-1 = <&pinctrl_i2c0_gpio>;
pinctrl-names = "default", "gpio";
sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c1 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
sda-gpios = <&pioA PIN_PD19 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PD20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
mcp16502@5b {
@ -258,12 +264,24 @@ pinctrl_i2c0_default: i2c0_default {
bias-disable;
};
pinctrl_i2c0_gpio: i2c0_gpio {
pinmux = <PIN_PD21__GPIO>,
<PIN_PD22__GPIO>;
bias-disable;
};
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PD19__TWD1>,
<PIN_PD20__TWCK1>;
bias-disable;
};
pinctrl_i2c1_gpio: i2c1_gpio {
pinmux = <PIN_PD19__GPIO>,
<PIN_PD20__GPIO>;
bias-disable;
};
pinctrl_macb0_default: macb0_default {
pinmux = <PIN_PB14__GTXCK>,
<PIN_PB15__GTXEN>,

1
arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts
View File

@ -209,7 +209,6 @@ &shutdown_controller {
input@0 {
reg = <0>;
atmel,wakeup-type = "low";
};
};

1
arch/arm/boot/dts/at91-sama5d2_icp.dts
View File

@ -697,7 +697,6 @@ &shutdown_controller {
input@0 {
reg = <0>;
atmel,wakeup-type = "low";
};
};

1
arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
View File

@ -206,7 +206,6 @@ shdwc@f8048010 {
input@0 {
reg = <0>;
atmel,wakeup-type = "low";
};
};

1
arch/arm/boot/dts/at91-sama5d2_xplained.dts
View File

@ -351,7 +351,6 @@ shdwc@f8048010 {
input@0 {
reg = <0>;
atmel,wakeup-type = "low";
};
};

78
arch/arm/boot/dts/atlas6-evb.dts
View File

@ -1,78 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DTS file for CSR SiRFatlas6 Evaluation Board
*
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
/dts-v1/;
/include/ "atlas6.dtsi"
/ {
model = "CSR SiRFatlas6 Evaluation Board";
compatible = "sirf,atlas6-cb", "sirf,atlas6";
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>;
};
axi {
peri-iobg {
uart@b0060000 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_a>;
};
spi@b00d0000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins_a>;
spi@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
spi@b0170000 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_a>;
};
i2c0: i2c@b00e0000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
lcd@40 {
compatible = "sirf,lcd";
reg = <0x40>;
};
};
};
disp-iobg {
lcd@90010000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&lcd_24pins_a>;
};
};
};
display: display@0 {
panels {
panel0: panel@0 {
panel-name = "Innolux TFT";
hactive = <800>;
vactive = <480>;
left_margin = <20>;
right_margin = <234>;
upper_margin = <3>;
lower_margin = <41>;
hsync_len = <3>;
vsync_len = <2>;
pixclock = <33264000>;
sync = <3>;
timing = <0x88>;
};
};
};
};

800
arch/arm/boot/dts/atlas6.dtsi
View File

@ -1,800 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DTS file for CSR SiRFatlas6 SoC
*
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
/ {
compatible = "sirf,atlas6";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
reg = <0x0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-size = <32768>;
/* from bootloader */
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
clocks = <&clks 12>;
operating-points = <
/* kHz uV */
200000 1025000
400000 1025000
600000 1050000
800000 1100000
>;
clock-latency = <150000>;
};
};
arm-pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <29>;
};
axi {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x40000000 0x40000000 0x80000000>;
intc: interrupt-controller@80020000 {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "sirf,prima2-intc";
reg = <0x80020000 0x1000>;
};
sys-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x88000000 0x88000000 0x40000>;
clks: clock-controller@88000000 {
compatible = "sirf,atlas6-clkc";
reg = <0x88000000 0x1000>;
interrupts = <3>;
#clock-cells = <1>;
};
rstc: reset-controller@88010000 {
compatible = "sirf,prima2-rstc";
reg = <0x88010000 0x1000>;
#reset-cells = <1>;
};
rsc-controller@88020000 {
compatible = "sirf,prima2-rsc";
reg = <0x88020000 0x1000>;
};
cphifbg@88030000 {
compatible = "sirf,prima2-cphifbg";
reg = <0x88030000 0x1000>;
clocks = <&clks 42>;
};
};
mem-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x90000000 0x90000000 0x10000>;
memory-controller@90000000 {
compatible = "sirf,prima2-memc";
reg = <0x90000000 0x2000>;
interrupts = <27>;
clocks = <&clks 5>;
};
memc-monitor {
compatible = "sirf,prima2-memcmon";
reg = <0x90002000 0x200>;
interrupts = <4>;
clocks = <&clks 32>;
};
};
disp-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x90010000 0x90010000 0x30000>;
lcd@90010000 {
compatible = "sirf,prima2-lcd";
reg = <0x90010000 0x20000>;
interrupts = <30>;
clocks = <&clks 34>;
display=<&display>;
/* later transfer to pwm */
bl-gpio = <&gpio 7 0>;
default-panel = <&panel0>;
};
vpp@90020000 {
compatible = "sirf,prima2-vpp";
reg = <0x90020000 0x10000>;
interrupts = <31>;
clocks = <&clks 35>;
resets = <&rstc 6>;
};
};
graphics-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x98000000 0x98000000 0x8000000>;
graphics@98000000 {
compatible = "powervr,sgx510";
reg = <0x98000000 0x8000000>;
interrupts = <6>;
clocks = <&clks 32>;
};
};
graphics2d-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xa0000000 0xa0000000 0x8000000>;
ble@a0000000 {
compatible = "sirf,atlas6-ble";
reg = <0xa0000000 0x2000>;
interrupts = <5>;
clocks = <&clks 33>;
};
};
dsp-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xa8000000 0xa8000000 0x2000000>;
dspif@a8000000 {
compatible = "sirf,prima2-dspif";
reg = <0xa8000000 0x10000>;
interrupts = <9>;
resets = <&rstc 1>;
};
gps@a8010000 {
compatible = "sirf,prima2-gps";
reg = <0xa8010000 0x10000>;
interrupts = <7>;
clocks = <&clks 9>;
resets = <&rstc 2>;
};
dsp@a9000000 {
compatible = "sirf,prima2-dsp";
reg = <0xa9000000 0x1000000>;
interrupts = <8>;
clocks = <&clks 8>;
resets = <&rstc 0>;
};
};
peri-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xb0000000 0xb0000000 0x180000>,
<0x56000000 0x56000000 0x1b00000>;
timer@b0020000 {
compatible = "sirf,prima2-tick";
reg = <0xb0020000 0x1000>;
interrupts = <0>;
clocks = <&clks 11>;
};
nand@b0030000 {
compatible = "sirf,prima2-nand";
reg = <0xb0030000 0x10000>;
interrupts = <41>;
clocks = <&clks 26>;
};
audio@b0040000 {
compatible = "sirf,prima2-audio";
reg = <0xb0040000 0x10000>;
interrupts = <35>;
clocks = <&clks 27>;
};
uart0: uart@b0050000 {
cell-index = <0>;
compatible = "sirf,prima2-uart";
reg = <0xb0050000 0x1000>;
interrupts = <17>;
fifosize = <128>;
clocks = <&clks 13>;
dmas = <&dmac1 5>, <&dmac0 2>;
dma-names = "rx", "tx";
};
uart1: uart@b0060000 {
cell-index = <1>;
compatible = "sirf,prima2-uart";
reg = <0xb0060000 0x1000>;
interrupts = <18>;
fifosize = <32>;
clocks = <&clks 14>;
dma-names = "no-rx", "no-tx";
};
uart2: uart@b0070000 {
cell-index = <2>;
compatible = "sirf,prima2-uart";
reg = <0xb0070000 0x1000>;
interrupts = <19>;
fifosize = <128>;
clocks = <&clks 15>;
dmas = <&dmac0 6>, <&dmac0 7>;
dma-names = "rx", "tx";
};
usp0: usp@b0080000 {
cell-index = <0>;
compatible = "sirf,prima2-usp";
reg = <0xb0080000 0x10000>;
interrupts = <20>;
fifosize = <128>;
clocks = <&clks 28>;
dmas = <&dmac1 1>, <&dmac1 2>;
dma-names = "rx", "tx";
};
usp1: usp@b0090000 {
cell-index = <1>;
compatible = "sirf,prima2-usp";
reg = <0xb0090000 0x10000>;
interrupts = <21>;
fifosize = <128>;
clocks = <&clks 29>;
dmas = <&dmac0 14>, <&dmac0 15>;
dma-names = "rx", "tx";
};
dmac0: dma-controller@b00b0000 {
cell-index = <0>;
compatible = "sirf,prima2-dmac";
reg = <0xb00b0000 0x10000>;
interrupts = <12>;
clocks = <&clks 24>;
#dma-cells = <1>;
};
dmac1: dma-controller@b0160000 {
cell-index = <1>;
compatible = "sirf,prima2-dmac";
reg = <0xb0160000 0x10000>;
interrupts = <13>;
clocks = <&clks 25>;
#dma-cells = <1>;
};
vip@b00C0000 {
compatible = "sirf,prima2-vip";
reg = <0xb00C0000 0x10000>;
clocks = <&clks 31>;
interrupts = <14>;
sirf,vip-dma-rx-channel = <16>;
};
spi0: spi@b00d0000 {
cell-index = <0>;
compatible = "sirf,prima2-spi";
reg = <0xb00d0000 0x10000>;
interrupts = <15>;
sirf,spi-num-chipselects = <1>;
dmas = <&dmac1 9>,
<&dmac1 4>;
dma-names = "rx", "tx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clks 19>;
resets = <&rstc 26>;
status = "disabled";
};
spi1: spi@b0170000 {
cell-index = <1>;
compatible = "sirf,prima2-spi";
reg = <0xb0170000 0x10000>;
interrupts = <16>;
sirf,spi-num-chipselects = <1>;
dmas = <&dmac0 12>,
<&dmac0 13>;
dma-names = "rx", "tx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clks 20>;
resets = <&rstc 27>;
status = "disabled";
};
i2c0: i2c@b00e0000 {
cell-index = <0>;
compatible = "sirf,prima2-i2c";
reg = <0xb00e0000 0x10000>;
interrupts = <24>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clks 17>;
};
i2c1: i2c@b00f0000 {
cell-index = <1>;
compatible = "sirf,prima2-i2c";
reg = <0xb00f0000 0x10000>;
interrupts = <25>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clks 18>;
};
tsc@b0110000 {
compatible = "sirf,prima2-tsc";
reg = <0xb0110000 0x10000>;
interrupts = <33>;
clocks = <&clks 16>;
};
gpio: pinctrl@b0120000 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "sirf,atlas6-pinctrl";
reg = <0xb0120000 0x10000>;
interrupts = <43 44 45 46 47>;
gpio-controller;
interrupt-controller;
lcd_16pins_a: lcd0@0 {
lcd {
sirf,pins = "lcd_16bitsgrp";
sirf,function = "lcd_16bits";
};
};
lcd_18pins_a: lcd0@1 {
lcd {
sirf,pins = "lcd_18bitsgrp";
sirf,function = "lcd_18bits";
};
};
lcd_24pins_a: lcd0@2 {
lcd {
sirf,pins = "lcd_24bitsgrp";
sirf,function = "lcd_24bits";
};
};
lcdrom_pins_a: lcdrom0@0 {
lcd {
sirf,pins = "lcdromgrp";
sirf,function = "lcdrom";
};
};
uart0_pins_a: uart0@0 {
uart {
sirf,pins = "uart0grp";
sirf,function = "uart0";
};
};
uart0_noflow_pins_a: uart0@1 {
uart {
sirf,pins = "uart0_nostreamctrlgrp";
sirf,function = "uart0_nostreamctrl";
};
};
uart1_pins_a: uart1@0 {
uart {
sirf,pins = "uart1grp";
sirf,function = "uart1";
};
};
uart2_pins_a: uart2@0 {
uart {
sirf,pins = "uart2grp";
sirf,function = "uart2";
};
};
uart2_noflow_pins_a: uart2@1 {
uart {
sirf,pins = "uart2_nostreamctrlgrp";
sirf,function = "uart2_nostreamctrl";
};
};
spi0_pins_a: spi0@0 {
spi {
sirf,pins = "spi0grp";
sirf,function = "spi0";
};
};
spi1_pins_a: spi1@0 {
spi {
sirf,pins = "spi1grp";
sirf,function = "spi1";
};
};
i2c0_pins_a: i2c0@0 {
i2c {
sirf,pins = "i2c0grp";
sirf,function = "i2c0";
};
};
i2c1_pins_a: i2c1@0 {
i2c {
sirf,pins = "i2c1grp";
sirf,function = "i2c1";
};
};
pwm0_pins_a: pwm0@0 {
pwm {
sirf,pins = "pwm0grp";
sirf,function = "pwm0";
};
};
pwm1_pins_a: pwm1@0 {
pwm {
sirf,pins = "pwm1grp";
sirf,function = "pwm1";
};
};
pwm2_pins_a: pwm2@0 {
pwm {
sirf,pins = "pwm2grp";
sirf,function = "pwm2";
};
};
pwm3_pins_a: pwm3@0 {
pwm {
sirf,pins = "pwm3grp";
sirf,function = "pwm3";
};
};
pwm4_pins_a: pwm4@0 {
pwm {
sirf,pins = "pwm4grp";
sirf,function = "pwm4";
};
};
gps_pins_a: gps@0 {
gps {
sirf,pins = "gpsgrp";
sirf,function = "gps";
};
};
vip_pins_a: vip@0 {
vip {
sirf,pins = "vipgrp";
sirf,function = "vip";
};
};
sdmmc0_pins_a: sdmmc0@0 {
sdmmc0 {
sirf,pins = "sdmmc0grp";
sirf,function = "sdmmc0";
};
};
sdmmc1_pins_a: sdmmc1@0 {
sdmmc1 {
sirf,pins = "sdmmc1grp";
sirf,function = "sdmmc1";
};
};
sdmmc2_pins_a: sdmmc2@0 {
sdmmc2 {
sirf,pins = "sdmmc2grp";
sirf,function = "sdmmc2";
};
};
sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
sdmmc2_nowp {
sirf,pins = "sdmmc2_nowpgrp";
sirf,function = "sdmmc2_nowp";
};
};
sdmmc3_pins_a: sdmmc3@0 {
sdmmc3 {
sirf,pins = "sdmmc3grp";
sirf,function = "sdmmc3";
};
};
sdmmc5_pins_a: sdmmc5@0 {
sdmmc5 {
sirf,pins = "sdmmc5grp";
sirf,function = "sdmmc5";
};
};
i2s_mclk_pins_a: i2s_mclk@0 {
i2s_mclk {
sirf,pins = "i2smclkgrp";
sirf,function = "i2s_mclk";
};
};
i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 {
i2s_ext_clk_input {
sirf,pins = "i2s_ext_clk_inputgrp";
sirf,function = "i2s_ext_clk_input";
};
};
i2s_pins_a: i2s@0 {
i2s {
sirf,pins = "i2sgrp";
sirf,function = "i2s";
};
};
i2s_no_din_pins_a: i2s_no_din@0 {
i2s_no_din {
sirf,pins = "i2s_no_dingrp";
sirf,function = "i2s_no_din";
};
};
i2s_6chn_pins_a: i2s_6chn@0 {
i2s_6chn {
sirf,pins = "i2s_6chngrp";
sirf,function = "i2s_6chn";
};
};
ac97_pins_a: ac97@0 {
ac97 {
sirf,pins = "ac97grp";
sirf,function = "ac97";
};
};
nand_pins_a: nand@0 {
nand {
sirf,pins = "nandgrp";
sirf,function = "nand";
};
};
usp0_pins_a: usp0@0 {
usp0 {
sirf,pins = "usp0grp";
sirf,function = "usp0";
};
};
usp0_uart_nostreamctrl_pins_a: usp0@1 {
usp0 {
sirf,pins = "usp0_uart_nostreamctrl_grp";
sirf,function = "usp0_uart_nostreamctrl";
};
};
usp0_only_utfs_pins_a: usp0@2 {
usp0 {
sirf,pins = "usp0_only_utfs_grp";
sirf,function = "usp0_only_utfs";
};
};
usp0_only_urfs_pins_a: usp0@3 {
usp0 {
sirf,pins = "usp0_only_urfs_grp";
sirf,function = "usp0_only_urfs";
};
};
usp1_pins_a: usp1@0 {
usp1 {
sirf,pins = "usp1grp";
sirf,function = "usp1";
};
};
usp1_uart_nostreamctrl_pins_a: usp1@1 {
usp1 {
sirf,pins = "usp1_uart_nostreamctrl_grp";
sirf,function = "usp1_uart_nostreamctrl";
};
};
usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
usb0_upli_drvbus {
sirf,pins = "usb0_upli_drvbusgrp";
sirf,function = "usb0_upli_drvbus";
};
};
usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
usb1_utmi_drvbus {
sirf,pins = "usb1_utmi_drvbusgrp";
sirf,function = "usb1_utmi_drvbus";
};
};
usb1_dp_dn_pins_a: usb1_dp_dn@0 {
usb1_dp_dn {
sirf,pins = "usb1_dp_dngrp";
sirf,function = "usb1_dp_dn";
};
};
uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
uart1_route_io_usb1 {
sirf,pins = "uart1_route_io_usb1grp";
sirf,function = "uart1_route_io_usb1";
};
};
warm_rst_pins_a: warm_rst@0 {
warm_rst {
sirf,pins = "warm_rstgrp";
sirf,function = "warm_rst";
};
};
pulse_count_pins_a: pulse_count@0 {
pulse_count {
sirf,pins = "pulse_countgrp";
sirf,function = "pulse_count";
};
};
cko0_pins_a: cko0@0 {
cko0 {
sirf,pins = "cko0grp";
sirf,function = "cko0";
};
};
cko1_pins_a: cko1@0 {
cko1 {
sirf,pins = "cko1grp";
sirf,function = "cko1";
};
};
};
pwm@b0130000 {
compatible = "sirf,prima2-pwm";
reg = <0xb0130000 0x10000>;
clocks = <&clks 21>;
};
efusesys@b0140000 {
compatible = "sirf,prima2-efuse";
reg = <0xb0140000 0x10000>;
clocks = <&clks 22>;
};
pulsec@b0150000 {
compatible = "sirf,prima2-pulsec";
reg = <0xb0150000 0x10000>;
interrupts = <48>;
clocks = <&clks 23>;
};
pci-iobg {
compatible = "sirf,prima2-pciiobg", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x56000000 0x56000000 0x1b00000>;
sd0: sdhci@56000000 {
cell-index = <0>;
compatible = "sirf,prima2-sdhc";
reg = <0x56000000 0x100000>;
interrupts = <38>;
bus-width = <8>;
clocks = <&clks 36>;
};
sd1: sdhci@56100000 {
cell-index = <1>;
compatible = "sirf,prima2-sdhc";
reg = <0x56100000 0x100000>;
interrupts = <38>;
status = "disabled";
bus-width = <4>;
clocks = <&clks 36>;
};
sd2: sdhci@56200000 {
cell-index = <2>;
compatible = "sirf,prima2-sdhc";
reg = <0x56200000 0x100000>;
interrupts = <23>;
status = "disabled";
bus-width = <4>;
clocks = <&clks 37>;
};
sd3: sdhci@56300000 {
cell-index = <3>;
compatible = "sirf,prima2-sdhc";
reg = <0x56300000 0x100000>;
interrupts = <23>;
status = "disabled";
bus-width = <4>;
clocks = <&clks 37>;
};
sd5: sdhci@56500000 {
cell-index = <5>;
compatible = "sirf,prima2-sdhc";
reg = <0x56500000 0x100000>;
interrupts = <39>;
status = "disabled";
bus-width = <4>;
clocks = <&clks 38>;
};
pci-copy@57900000 {
compatible = "sirf,prima2-pcicp";
reg = <0x57900000 0x100000>;
interrupts = <40>;
};
rom-interface@57a00000 {
compatible = "sirf,prima2-romif";
reg = <0x57a00000 0x100000>;
};
};
};
rtc-iobg {
compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80030000 0x10000>;
gpsrtc@1000 {
compatible = "sirf,prima2-gpsrtc";
reg = <0x1000 0x1000>;
interrupts = <55 56 57>;
};
sysrtc@2000 {
compatible = "sirf,prima2-sysrtc";
reg = <0x2000 0x1000>;
interrupts = <52 53 54>;
};
minigpsrtc@2000 {
compatible = "sirf,prima2-minigpsrtc";
reg = <0x2000 0x1000>;
interrupts = <54>;
};
pwrc@3000 {
compatible = "sirf,prima2-pwrc";
reg = <0x3000 0x1000>;
interrupts = <32>;
};
};
uus-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xb8000000 0xb8000000 0x40000>;
usb0: usb@b00e0000 {
compatible = "chipidea,ci13611a-prima2";
reg = <0xb8000000 0x10000>;
interrupts = <10>;
clocks = <&clks 40>;
};
usb1: usb@b00f0000 {
compatible = "chipidea,ci13611a-prima2";
reg = <0xb8010000 0x10000>;
interrupts = <11>;
clocks = <&clks 41>;
};
security@b00f0000 {
compatible = "sirf,prima2-security";
reg = <0xb8030000 0x10000>;
interrupts = <42>;
clocks = <&clks 7>;
};
};
};
};

127
arch/arm/boot/dts/atlas7-evb.dts
View File

@ -1,127 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DTS file for CSR SiRFatlas7 Evaluation Board
*
* Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
/dts-v1/;
/include/ "atlas7.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "CSR SiRFatlas7 Evaluation Board";
compatible = "sirf,atlas7-cb", "sirf,atlas7";
chosen {
bootargs = "console=ttySiRF1,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x40000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
vpp_reserved: vpp_mem@5e800000 {
compatible = "sirf,reserved-memory";
reg = <0x5e800000 0x800000>;
};
nanddisk_reserved: nanddisk@46000000 {
reg = <0x46000000 0x200000>;
no-map;
};
};
noc {
mediam {
nand@17050000 {
memory-region = <&nanddisk_reserved>;
};
};
gnssm {
spi1: spi@18200000 {
status = "okay";
spiflash: macronix@0{
status = "okay";
compatible = "macronix,mx25l6405d";
reg = <0>;
spi-max-frequency = <37500000>;
spi-cpha;
spi-cpol;
#address-cells = <1>;
#size-cells = <1>;
partitions@0 {
label = "myspiboot";
reg = <0x0 0x800000>;
};
};
};
};
btm {
uart6: uart@11000000 {
status = "okay";
uart-has-rtscts;
};
};
disp-iobg {
vpp@13110000 {
memory-region = <&vpp_reserved>;
};
};
display0: display@0 {
compatible = "lvds-panel";
source = "lvds.0";
bl-gpios = <&gpio_1 63 0>;
data-lines = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <60000000>;
hactive = <1024>;
vactive = <600>;
hfront-porch = <220>;
hback-porch = <100>;
hsync-len = <1>;
vback-porch = <10>;
vfront-porch = <25>;
vsync-len = <1>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
gpio_keys {
compatible = "gpio-keys";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
rearview_key {
label = "rearview key";
linux,code = <KEY_CAMERA>;
gpios = <&gpio_1 3 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
};
};
};

1955
arch/arm/boot/dts/atlas7.dtsi
View File

File diff suppressed because it is too large Load Diff

2
arch/arm/boot/dts/bcm21664.dtsi
View File

@ -27,7 +27,7 @@ chosen {
bootargs = "console=ttyS0,115200n8";
};
cpus {
cpus {
#address-cells = <1>;
#size-cells = <0>;

17
arch/arm/boot/dts/bcm2711-rpi-4-b.dts
View File

@ -25,6 +25,7 @@ aliases {
emmc2bus = &emmc2bus;
ethernet0 = &genet;
pcie0 = &pcie0;
blconfig = &blconfig;
};
leds {
@ -218,6 +219,22 @@ &pwm1 {
status = "okay";
};
&rmem {
/*
* RPi4's co-processor will copy the board's bootloader configuration
* into memory for the OS to consume. It'll also update this node with
* its placement information.
*/
blconfig: nvram@0 {
compatible = "raspberrypi,bootloader-config", "nvmem-rmem";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x0 0x0>;
no-map;
status = "disabled";
};
};
/* SDHCI is used to control the SDIO for wireless */
&sdhci {
#address-cells = <1>;

31
arch/arm/boot/dts/bcm2711.dtsi
View File

@ -308,6 +308,22 @@ dvp: clock@7ef00000 {
#reset-cells = <1>;
};
bsc_intr: interrupt-controller@7ef00040 {
compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
reg = <0x7ef00040 0x30>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
};
aon_intr: interrupt-controller@7ef00100 {
compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
reg = <0x7ef00100 0x30>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
};
hdmi0: hdmi@7ef00700 {
compatible = "brcm,bcm2711-hdmi0";
reg = <0x7ef00700 0x300>,
@ -330,6 +346,11 @@ hdmi0: hdmi@7ef00700 {
"hd";
clock-names = "hdmi", "bvb", "audio", "cec";
resets = <&dvp 0>;
interrupt-parent = <&aon_intr>;
interrupts = <0>, <1>, <2>,
<3>, <4>, <5>;
interrupt-names = "cec-tx", "cec-rx", "cec-low",
"wakeup", "hpd-connected", "hpd-removed";
ddc = <&ddc0>;
dmas = <&dma 10>;
dma-names = "audio-rx";
@ -341,6 +362,8 @@ ddc0: i2c@7ef04500 {
reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
reg-names = "bsc", "auto-i2c";
clock-frequency = <97500>;
interrupt-parent = <&bsc_intr>;
interrupts = <0>;
status = "disabled";
};
@ -367,6 +390,11 @@ hdmi1: hdmi@7ef05700 {
ddc = <&ddc1>;
clock-names = "hdmi", "bvb", "audio", "cec";
resets = <&dvp 1>;
interrupt-parent = <&aon_intr>;
interrupts = <8>, <7>, <6>,
<9>, <10>, <11>;
interrupt-names = "cec-tx", "cec-rx", "cec-low",
"wakeup", "hpd-connected", "hpd-removed";
dmas = <&dma 17>;
dma-names = "audio-rx";
status = "disabled";
@ -377,6 +405,8 @@ ddc1: i2c@7ef09500 {
reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
reg-names = "bsc", "auto-i2c";
clock-frequency = <97500>;
interrupt-parent = <&bsc_intr>;
interrupts = <1>;
status = "disabled";
};
};
@ -540,6 +570,7 @@ &dsi0 {
&dsi1 {
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
compatible = "brcm,bcm2711-dsi1";
};
&gpio {

12
arch/arm/boot/dts/berlin2.dtsi
View File

@ -191,7 +191,7 @@ porta: gpio-port@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
ngpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@ -209,7 +209,7 @@ portb: gpio-port@1 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
ngpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@ -227,7 +227,7 @@ portc: gpio-port@2 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
ngpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@ -245,7 +245,7 @@ portd: gpio-port@3 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
ngpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@ -446,7 +446,7 @@ portf: gpio-port@5 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
ngpios = <8>;
reg = <0>;
};
};
@ -461,7 +461,7 @@ porte: gpio-port@4 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
ngpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;

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