CRIS v32: Remove kernel/arbiter.c, it now exists in machine dependent directory.
This commit is contained in:
Jesper Nilsson
parent
1791f539cd
commit
a87434b04f
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/*
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* Memory arbiter functions. Allocates bandwidth through the
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* arbiter and sets up arbiter breakpoints.
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*
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* The algorithm first assigns slots to the clients that has specified
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* bandwidth (e.g. ethernet) and then the remaining slots are divided
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* on all the active clients.
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*
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* Copyright (c) 2004, 2005 Axis Communications AB.
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*/
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#include <asm/arch/hwregs/reg_map.h>
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#include <asm/arch/hwregs/reg_rdwr.h>
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#include <asm/arch/hwregs/marb_defs.h>
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#include <asm/arch/arbiter.h>
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#include <asm/arch/hwregs/intr_vect.h>
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#include <linux/interrupt.h>
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#include <linux/signal.h>
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#include <linux/errno.h>
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#include <linux/spinlock.h>
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#include <asm/io.h>
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struct crisv32_watch_entry
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{
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unsigned long instance;
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watch_callback* cb;
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unsigned long start;
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unsigned long end;
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int used;
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};
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#define NUMBER_OF_BP 4
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#define NBR_OF_CLIENTS 14
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#define NBR_OF_SLOTS 64
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#define SDRAM_BANDWIDTH 100000000 /* Some kind of expected value */
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#define INTMEM_BANDWIDTH 400000000
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#define NBR_OF_REGIONS 2
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static struct crisv32_watch_entry watches[NUMBER_OF_BP] =
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{
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{regi_marb_bp0},
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{regi_marb_bp1},
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{regi_marb_bp2},
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{regi_marb_bp3}
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};
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static int requested_slots[NBR_OF_REGIONS][NBR_OF_CLIENTS];
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static int active_clients[NBR_OF_REGIONS][NBR_OF_CLIENTS];
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static int max_bandwidth[NBR_OF_REGIONS] = {SDRAM_BANDWIDTH, INTMEM_BANDWIDTH};
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DEFINE_SPINLOCK(arbiter_lock);
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static irqreturn_t
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crisv32_arbiter_irq(int irq, void* dev_id, struct pt_regs* regs);
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static void crisv32_arbiter_config(int region)
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{
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int slot;
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int client;
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int interval = 0;
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int val[NBR_OF_SLOTS];
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for (slot = 0; slot < NBR_OF_SLOTS; slot++)
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val[slot] = NBR_OF_CLIENTS + 1;
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for (client = 0; client < NBR_OF_CLIENTS; client++)
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{
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int pos;
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if (!requested_slots[region][client])
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continue;
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interval = NBR_OF_SLOTS / requested_slots[region][client];
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pos = 0;
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while (pos < NBR_OF_SLOTS)
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{
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if (val[pos] != NBR_OF_CLIENTS + 1)
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pos++;
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else
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{
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val[pos] = client;
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pos += interval;
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}
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}
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}
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client = 0;
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for (slot = 0; slot < NBR_OF_SLOTS; slot++)
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{
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if (val[slot] == NBR_OF_CLIENTS + 1)
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{
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int first = client;
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while(!active_clients[region][client]) {
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client = (client + 1) % NBR_OF_CLIENTS;
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if (client == first)
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break;
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}
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val[slot] = client;
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client = (client + 1) % NBR_OF_CLIENTS;
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}
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if (region == EXT_REGION)
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REG_WR_INT_VECT(marb, regi_marb, rw_ext_slots, slot, val[slot]);
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else if (region == INT_REGION)
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REG_WR_INT_VECT(marb, regi_marb, rw_int_slots, slot, val[slot]);
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}
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}
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extern char _stext, _etext;
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static void crisv32_arbiter_init(void)
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{
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static int initialized = 0;
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if (initialized)
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return;
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initialized = 1;
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/* CPU caches are active. */
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active_clients[EXT_REGION][10] = active_clients[EXT_REGION][11] = 1;
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crisv32_arbiter_config(EXT_REGION);
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crisv32_arbiter_config(INT_REGION);
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if (request_irq(MEMARB_INTR_VECT, crisv32_arbiter_irq, IRQF_DISABLED,
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"arbiter", NULL))
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printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
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#ifndef CONFIG_ETRAX_KGDB
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/* Global watch for writes to kernel text segment. */
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crisv32_arbiter_watch(virt_to_phys(&_stext), &_etext - &_stext,
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arbiter_all_clients, arbiter_all_write, NULL);
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#endif
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}
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int crisv32_arbiter_allocate_bandwidth(int client, int region,
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unsigned long bandwidth)
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{
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int i;
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int total_assigned = 0;
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int total_clients = 0;
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int req;
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crisv32_arbiter_init();
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for (i = 0; i < NBR_OF_CLIENTS; i++)
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{
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total_assigned += requested_slots[region][i];
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total_clients += active_clients[region][i];
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}
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req = NBR_OF_SLOTS / (max_bandwidth[region] / bandwidth);
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if (total_assigned + total_clients + req + 1 > NBR_OF_SLOTS)
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return -ENOMEM;
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active_clients[region][client] = 1;
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requested_slots[region][client] = req;
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crisv32_arbiter_config(region);
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return 0;
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}
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int crisv32_arbiter_watch(unsigned long start, unsigned long size,
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unsigned long clients, unsigned long accesses,
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watch_callback* cb)
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{
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int i;
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crisv32_arbiter_init();
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if (start > 0x80000000) {
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printk("Arbiter: %lX doesn't look like a physical address", start);
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return -EFAULT;
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}
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spin_lock(&arbiter_lock);
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for (i = 0; i < NUMBER_OF_BP; i++) {
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if (!watches[i].used) {
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reg_marb_rw_intr_mask intr_mask = REG_RD(marb, regi_marb, rw_intr_mask);
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watches[i].used = 1;
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watches[i].start = start;
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watches[i].end = start + size;
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watches[i].cb = cb;
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REG_WR_INT(marb_bp, watches[i].instance, rw_first_addr, watches[i].start);
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REG_WR_INT(marb_bp, watches[i].instance, rw_last_addr, watches[i].end);
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REG_WR_INT(marb_bp, watches[i].instance, rw_op, accesses);
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REG_WR_INT(marb_bp, watches[i].instance, rw_clients, clients);
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if (i == 0)
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intr_mask.bp0 = regk_marb_yes;
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else if (i == 1)
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intr_mask.bp1 = regk_marb_yes;
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else if (i == 2)
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intr_mask.bp2 = regk_marb_yes;
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else if (i == 3)
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intr_mask.bp3 = regk_marb_yes;
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REG_WR(marb, regi_marb, rw_intr_mask, intr_mask);
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spin_unlock(&arbiter_lock);
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return i;
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}
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}
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spin_unlock(&arbiter_lock);
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return -ENOMEM;
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}
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int crisv32_arbiter_unwatch(int id)
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{
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reg_marb_rw_intr_mask intr_mask = REG_RD(marb, regi_marb, rw_intr_mask);
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crisv32_arbiter_init();
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spin_lock(&arbiter_lock);
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if ((id < 0) || (id >= NUMBER_OF_BP) || (!watches[id].used)) {
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spin_unlock(&arbiter_lock);
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return -EINVAL;
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}
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memset(&watches[id], 0, sizeof(struct crisv32_watch_entry));
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if (id == 0)
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intr_mask.bp0 = regk_marb_no;
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else if (id == 1)
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intr_mask.bp2 = regk_marb_no;
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else if (id == 2)
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intr_mask.bp2 = regk_marb_no;
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else if (id == 3)
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intr_mask.bp3 = regk_marb_no;
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REG_WR(marb, regi_marb, rw_intr_mask, intr_mask);
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spin_unlock(&arbiter_lock);
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return 0;
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}
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extern void show_registers(struct pt_regs *regs);
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static irqreturn_t
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crisv32_arbiter_irq(int irq, void* dev_id, struct pt_regs* regs)
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{
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reg_marb_r_masked_intr masked_intr = REG_RD(marb, regi_marb, r_masked_intr);
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reg_marb_bp_r_brk_clients r_clients;
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reg_marb_bp_r_brk_addr r_addr;
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reg_marb_bp_r_brk_op r_op;
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reg_marb_bp_r_brk_first_client r_first;
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reg_marb_bp_r_brk_size r_size;
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reg_marb_bp_rw_ack ack = {0};
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reg_marb_rw_ack_intr ack_intr = {.bp0=1,.bp1=1,.bp2=1,.bp3=1};
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struct crisv32_watch_entry* watch;
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if (masked_intr.bp0) {
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watch = &watches[0];
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ack_intr.bp0 = regk_marb_yes;
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} else if (masked_intr.bp1) {
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watch = &watches[1];
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ack_intr.bp1 = regk_marb_yes;
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} else if (masked_intr.bp2) {
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watch = &watches[2];
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ack_intr.bp2 = regk_marb_yes;
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} else if (masked_intr.bp3) {
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watch = &watches[3];
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ack_intr.bp3 = regk_marb_yes;
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} else {
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return IRQ_NONE;
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}
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/* Retrieve all useful information and print it. */
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r_clients = REG_RD(marb_bp, watch->instance, r_brk_clients);
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r_addr = REG_RD(marb_bp, watch->instance, r_brk_addr);
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r_op = REG_RD(marb_bp, watch->instance, r_brk_op);
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r_first = REG_RD(marb_bp, watch->instance, r_brk_first_client);
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r_size = REG_RD(marb_bp, watch->instance, r_brk_size);
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printk("Arbiter IRQ\n");
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printk("Clients %X addr %X op %X first %X size %X\n",
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REG_TYPE_CONV(int, reg_marb_bp_r_brk_clients, r_clients),
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REG_TYPE_CONV(int, reg_marb_bp_r_brk_addr, r_addr),
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REG_TYPE_CONV(int, reg_marb_bp_r_brk_op, r_op),
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REG_TYPE_CONV(int, reg_marb_bp_r_brk_first_client, r_first),
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REG_TYPE_CONV(int, reg_marb_bp_r_brk_size, r_size));
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REG_WR(marb_bp, watch->instance, rw_ack, ack);
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REG_WR(marb, regi_marb, rw_ack_intr, ack_intr);
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printk("IRQ occured at %lX\n", regs->erp);
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if (watch->cb)
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watch->cb();
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return IRQ_HANDLED;
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}
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