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ARM: tegra: don't unlock MMIO access to DBGLAR 

There is no need to unlock MMIO access to the DBGLAR all the time. Doing
so may even cause problems if a SW bug causes writes to that MMIO region.

Cortex-A15 processors do not support the CP14 register write the code
currently uses to unlock the DBGLAR; the instruction throws an undefined
instruction exceptions. This prevents tegra_secondary_startup() from
executing on Tegra114, and hence prevents SMP.

Remove the code that unlocks this access.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Joseph Lo 2013-02-19 18:16:13 +08:00 committed by Stephen Warren
parent bf161d2163
commit b095ae2b9f
2 changed files with 0 additions and 6 deletions
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3
arch/arm/mach-tegra/headsmp.S
View File

@ -7,8 +7,5 @@
ENTRY(tegra_secondary_startup) ENTRY(tegra_secondary_startup)
bl v7_invalidate_l1 bl v7_invalidate_l1
/* Enable coresight */
mov32 r0, 0xC5ACCE55
mcr p14, 0, r0, c7, c12, 6
b secondary_startup b secondary_startup
ENDPROC(tegra_secondary_startup) ENDPROC(tegra_secondary_startup)

3
arch/arm/mach-tegra/reset-handler.S
View File

@ -41,9 +41,6 @@
*/ */
ENTRY(tegra_resume) ENTRY(tegra_resume)
bl v7_invalidate_l1 bl v7_invalidate_l1
/* Enable coresight */
mov32 r0, 0xC5ACCE55
mcr p14, 0, r0, c7, c12, 6
cpu_id r0 cpu_id r0
cmp r0, #0 @ CPU0? cmp r0, #0 @ CPU0?