clk: renesas: Updates for v5.5 (take two)
- Switch some clocks on R-Car Gen2/3 to .determine_rate(), - Add support for the new R-Car M3-W+ (r8a77961) SoC, - Minor fixes and cleanups. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCXbxIQAAKCRCKwlD9ZEnx cPRKAP0YFKD+1w05E8P4S0qYcxsh+7RdYtbRotn8/5RP9P+9QgD/QMkJtw4AIVjR rOEp1FIdq6dQ0YNtoI+xKqCwkAUvog0= =4FXG -----END PGP SIGNATURE----- Merge tag 'clk-renesas-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Switch some clocks on R-Car Gen2/3 to .determine_rate() - Add support for the new R-Car M3-W+ (r8a77961) SoC - Add support for the new RZ/G2N (r8a774b1) SoC - Remove R-Car Gen2 legacy DT clock support - Improve arithmetic divisions on R-Car Gen2 and Gen3 - Improve R-Car Gen3 SD clock handling * tag 'clk-renesas-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (23 commits) clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960 dt-bindings: clock: renesas: cpg-mssr: Document r8a77961 support clk: renesas: r8a77965: Remove superfluous semicolon dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix typo in example dt-bindings: clock: renesas: Remove R-Car Gen2 legacy DT bindings dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions dt-bindings: power: Add r8a77961 SYSC power domain definitions clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate() clk: renesas: rcar-gen3: Switch Z clocks to .determine_rate() clk: renesas: rcar-gen2: Switch Z clock to .determine_rate() clk: renesas: r8a774b1: Add TMU clock clk: renesas: cpg-mssr: Add r8a774b1 support dt-bindings: clock: renesas: cpg-mssr: Document r8a774b1 binding clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate() clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div() clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate() clk: renesas: rcar-gen3: Improve arithmetic divisions clk: renesas: rcar-gen2: Improve arithmetic divisions clk: renesas: Remove R-Car Gen2 legacy DT clock support ...
This commit is contained in:
Stephen Boyd
commit
b7c1b40abc
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@ -19,6 +19,7 @@ Required Properties:
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- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
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- "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
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- "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)
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- "renesas,r8a774b1-cpg-mssr" for the r8a774a1 SoC (RZ/G2N)
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- "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)
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- "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
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- "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
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@ -26,7 +27,8 @@ Required Properties:
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- "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
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- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
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- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
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- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
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- "renesas,r8a7796-cpg-mssr" for the r8a77960 SoC (R-Car M3-W)
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- "renesas,r8a77961-cpg-mssr" for the r8a77961 SoC (R-Car M3-W+)
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- "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
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- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
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- "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
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@ -40,10 +42,11 @@ Required Properties:
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clock-names
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- clock-names: List of external parent clock names. Valid names are:
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- "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1,
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r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
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r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77990,
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r8a77995)
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- "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
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r8a774b1, r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793,
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r8a7794, r8a7795, r8a77960, r8a77961, r8a77965, r8a77970,
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r8a77980, r8a77990, r8a77995)
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- "extalr" (r8a774a1, r8a774b1, r8a7795, r8a77960, r8a77961, r8a77965,
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r8a77970, r8a77980)
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- "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791,
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r8a7793, r8a7794)
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@ -1,60 +0,0 @@
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* Renesas R-Car Gen2 Clock Pulse Generator (CPG)
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The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
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and several fixed ratio dividers.
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The CPG also provides a Clock Domain for SoC devices, in combination with the
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CPG Module Stop (MSTP) Clocks.
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Required Properties:
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- compatible: Must be one of
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- "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
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- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
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- "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG
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- "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
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- "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
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and "renesas,rcar-gen2-cpg-clocks" as a fallback.
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- reg: Base address and length of the memory resource used by the CPG
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- clocks: References to the parent clocks: first to the EXTAL clock, second
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to the USB_EXTAL clock
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are "main",
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"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
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"adsp"
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- #power-domain-cells: Must be 0
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SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
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through an MSTP clock should refer to the CPG device node in their
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"power-domains" property, as documented by the generic PM domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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Examples
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--------
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- CPG device node:
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7790-cpg-clocks",
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"renesas,rcar-gen2-cpg-clocks";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk &usb_extal_clk>;
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#clock-cells = <1>;
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clock-output-names = "main", "pll0, "pll1", "pll3",
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"lb", "qspi", "sdh", "sd0", "sd1", "z",
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"rcan", "adsp";
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#power-domain-cells = <0>;
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};
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- CPG/MSTP Clock Domain member device node:
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thermal@e61f0000 {
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compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
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reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
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interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
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power-domains = <&cpg_clocks>;
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};
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@ -46,7 +46,7 @@ Required properties:
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Example (R-Car H3):
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usb2_clksel: clock-controller@e6590630 {
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compatible = "renesas,r8a77950-rcar-usb2-clock-sel",
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compatible = "renesas,r8a7795-rcar-usb2-clock-sel",
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"renesas,rcar-gen3-usb2-clock-sel";
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reg = <0 0xe6590630 0 0x02>;
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clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;
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@ -12,6 +12,7 @@ config CLK_RENESAS
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select CLK_R8A7745 if ARCH_R8A7745
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select CLK_R8A77470 if ARCH_R8A77470
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select CLK_R8A774A1 if ARCH_R8A774A1
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select CLK_R8A774B1 if ARCH_R8A774B1
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select CLK_R8A774C0 if ARCH_R8A774C0
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select CLK_R8A7778 if ARCH_R8A7778
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select CLK_R8A7779 if ARCH_R8A7779
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@ -20,7 +21,8 @@ config CLK_RENESAS
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select CLK_R8A7792 if ARCH_R8A7792
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select CLK_R8A7794 if ARCH_R8A7794
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select CLK_R8A7795 if ARCH_R8A7795
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select CLK_R8A7796 if ARCH_R8A7796
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select CLK_R8A77960 if ARCH_R8A77960 || ARCH_R8A7796
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select CLK_R8A77961 if ARCH_R8A77961
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select CLK_R8A77965 if ARCH_R8A77965
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select CLK_R8A77970 if ARCH_R8A77970
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select CLK_R8A77980 if ARCH_R8A77980
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@ -31,17 +33,6 @@ config CLK_RENESAS
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if CLK_RENESAS
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config CLK_RENESAS_LEGACY
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bool "Legacy DT clock support"
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depends on CLK_R8A7790 || CLK_R8A7791 || CLK_R8A7792 || CLK_R8A7794
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help
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Enable backward compatibility with old device trees describing a
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hierarchical representation of the various CPG and MSTP clocks.
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Say Y if you want your kernel to work with old DTBs.
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It is safe to say N if you use the DTS that is supplied with the
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current kernel source tree.
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# SoC
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config CLK_EMEV2
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bool "Emma Mobile EV2 clock support" if COMPILE_TEST
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@ -80,6 +71,10 @@ config CLK_R8A774A1
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bool "RZ/G2M clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A774B1
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bool "RZ/G2N clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A774C0
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bool "RZ/G2E clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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@ -94,24 +89,20 @@ config CLK_R8A7779
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config CLK_R8A7790
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bool "R-Car H2 clock support" if COMPILE_TEST
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select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
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select CLK_RCAR_GEN2_CPG
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select CLK_RENESAS_DIV6
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config CLK_R8A7791
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bool "R-Car M2-W/N clock support" if COMPILE_TEST
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select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
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select CLK_RCAR_GEN2_CPG
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select CLK_RENESAS_DIV6
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config CLK_R8A7792
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bool "R-Car V2H clock support" if COMPILE_TEST
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select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
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select CLK_RCAR_GEN2_CPG
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config CLK_R8A7794
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bool "R-Car E2 clock support" if COMPILE_TEST
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select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
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select CLK_RCAR_GEN2_CPG
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select CLK_RENESAS_DIV6
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@ -119,10 +110,14 @@ config CLK_R8A7795
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bool "R-Car H3 clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A7796
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config CLK_R8A77960
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bool "R-Car M3-W clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A77961
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bool "R-Car M3-W+ clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A77965
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bool "R-Car M3-N clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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@ -155,11 +150,6 @@ config CLK_SH73A0
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# Family
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config CLK_RCAR_GEN2
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bool "R-Car Gen2 legacy clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSTP
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select CLK_RENESAS_DIV6
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config CLK_RCAR_GEN2_CPG
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bool "R-Car Gen2 CPG clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSSR
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|
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@ -9,6 +9,7 @@ obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o
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obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o
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@ -17,7 +18,8 @@ obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77960) += r8a7796-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77961) += r8a7796-cpg-mssr.o
|
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obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
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||||
obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
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||||
|
|
@ -27,7 +29,6 @@ obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
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obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
|
||||
|
||||
# Family
|
||||
obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
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obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o
|
||||
obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o
|
||||
obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o
|
||||
|
|
|
|||
|
|
@ -189,10 +189,8 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
|
|||
unsigned int i;
|
||||
|
||||
group = kzalloc(struct_size(group, clks, MSTP_MAX_CLOCKS), GFP_KERNEL);
|
||||
if (group == NULL) {
|
||||
kfree(group);
|
||||
if (!group)
|
||||
return;
|
||||
}
|
||||
|
||||
clks = group->clks;
|
||||
spin_lock_init(&group->lock);
|
||||
|
|
|
|||
|
|
@ -1,457 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* rcar_gen2 Core CPG Clocks
|
||||
*
|
||||
* Copyright (C) 2013 Ideas On Board SPRL
|
||||
*
|
||||
* Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/renesas.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/math64.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/soc/renesas/rcar-rst.h>
|
||||
|
||||
struct rcar_gen2_cpg {
|
||||
struct clk_onecell_data data;
|
||||
spinlock_t lock;
|
||||
void __iomem *reg;
|
||||
};
|
||||
|
||||
#define CPG_FRQCRB 0x00000004
|
||||
#define CPG_FRQCRB_KICK BIT(31)
|
||||
#define CPG_SDCKCR 0x00000074
|
||||
#define CPG_PLL0CR 0x000000d8
|
||||
#define CPG_FRQCRC 0x000000e0
|
||||
#define CPG_FRQCRC_ZFC_MASK (0x1f << 8)
|
||||
#define CPG_FRQCRC_ZFC_SHIFT 8
|
||||
#define CPG_ADSPCKCR 0x0000025c
|
||||
#define CPG_RCANCKCR 0x00000270
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Z Clock
|
||||
*
|
||||
* Traits of this clock:
|
||||
* prepare - clk_prepare only ensures that parents are prepared
|
||||
* enable - clk_enable only ensures that parents are enabled
|
||||
* rate - rate is adjustable. clk->rate = parent->rate * mult / 32
|
||||
* parent - fixed parent. No clk_set_parent support
|
||||
*/
|
||||
|
||||
struct cpg_z_clk {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
void __iomem *kick_reg;
|
||||
};
|
||||
|
||||
#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
|
||||
|
||||
static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct cpg_z_clk *zclk = to_z_clk(hw);
|
||||
unsigned int mult;
|
||||
unsigned int val;
|
||||
|
||||
val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT;
|
||||
mult = 32 - val;
|
||||
|
||||
return div_u64((u64)parent_rate * mult, 32);
|
||||
}
|
||||
|
||||
static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
unsigned long prate = *parent_rate;
|
||||
unsigned int mult;
|
||||
|
||||
if (!prate)
|
||||
prate = 1;
|
||||
|
||||
mult = div_u64((u64)rate * 32, prate);
|
||||
mult = clamp(mult, 1U, 32U);
|
||||
|
||||
return *parent_rate / 32 * mult;
|
||||
}
|
||||
|
||||
static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct cpg_z_clk *zclk = to_z_clk(hw);
|
||||
unsigned int mult;
|
||||
u32 val, kick;
|
||||
unsigned int i;
|
||||
|
||||
mult = div_u64((u64)rate * 32, parent_rate);
|
||||
mult = clamp(mult, 1U, 32U);
|
||||
|
||||
if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
|
||||
return -EBUSY;
|
||||
|
||||
val = readl(zclk->reg);
|
||||
val &= ~CPG_FRQCRC_ZFC_MASK;
|
||||
val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
|
||||
writel(val, zclk->reg);
|
||||
|
||||
/*
|
||||
* Set KICK bit in FRQCRB to update hardware setting and wait for
|
||||
* clock change completion.
|
||||
*/
|
||||
kick = readl(zclk->kick_reg);
|
||||
kick |= CPG_FRQCRB_KICK;
|
||||
writel(kick, zclk->kick_reg);
|
||||
|
||||
/*
|
||||
* Note: There is no HW information about the worst case latency.
|
||||
*
|
||||
* Using experimental measurements, it seems that no more than
|
||||
* ~10 iterations are needed, independently of the CPU rate.
|
||||
* Since this value might be dependent on external xtal rate, pll1
|
||||
* rate or even the other emulation clocks rate, use 1000 as a
|
||||
* "super" safe value.
|
||||
*/
|
||||
for (i = 1000; i; i--) {
|
||||
if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
|
||||
return 0;
|
||||
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static const struct clk_ops cpg_z_clk_ops = {
|
||||
.recalc_rate = cpg_z_clk_recalc_rate,
|
||||
.round_rate = cpg_z_clk_round_rate,
|
||||
.set_rate = cpg_z_clk_set_rate,
|
||||
};
|
||||
|
||||
static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg)
|
||||
{
|
||||
static const char *parent_name = "pll0";
|
||||
struct clk_init_data init;
|
||||
struct cpg_z_clk *zclk;
|
||||
struct clk *clk;
|
||||
|
||||
zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
|
||||
if (!zclk)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = "z";
|
||||
init.ops = &cpg_z_clk_ops;
|
||||
init.flags = 0;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
zclk->reg = cpg->reg + CPG_FRQCRC;
|
||||
zclk->kick_reg = cpg->reg + CPG_FRQCRB;
|
||||
zclk->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &zclk->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(zclk);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
static struct clk * __init cpg_rcan_clk_register(struct rcar_gen2_cpg *cpg,
|
||||
struct device_node *np)
|
||||
{
|
||||
const char *parent_name = of_clk_get_parent_name(np, 1);
|
||||
struct clk_fixed_factor *fixed;
|
||||
struct clk_gate *gate;
|
||||
struct clk *clk;
|
||||
|
||||
fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
|
||||
if (!fixed)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
fixed->mult = 1;
|
||||
fixed->div = 6;
|
||||
|
||||
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
||||
if (!gate) {
|
||||
kfree(fixed);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
gate->reg = cpg->reg + CPG_RCANCKCR;
|
||||
gate->bit_idx = 8;
|
||||
gate->flags = CLK_GATE_SET_TO_DISABLE;
|
||||
gate->lock = &cpg->lock;
|
||||
|
||||
clk = clk_register_composite(NULL, "rcan", &parent_name, 1, NULL, NULL,
|
||||
&fixed->hw, &clk_fixed_factor_ops,
|
||||
&gate->hw, &clk_gate_ops, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(gate);
|
||||
kfree(fixed);
|
||||
}
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
/* ADSP divisors */
|
||||
static const struct clk_div_table cpg_adsp_div_table[] = {
|
||||
{ 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 },
|
||||
{ 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
|
||||
{ 10, 36 }, { 11, 48 }, { 0, 0 },
|
||||
};
|
||||
|
||||
static struct clk * __init cpg_adsp_clk_register(struct rcar_gen2_cpg *cpg)
|
||||
{
|
||||
const char *parent_name = "pll1";
|
||||
struct clk_divider *div;
|
||||
struct clk_gate *gate;
|
||||
struct clk *clk;
|
||||
|
||||
div = kzalloc(sizeof(*div), GFP_KERNEL);
|
||||
if (!div)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
div->reg = cpg->reg + CPG_ADSPCKCR;
|
||||
div->width = 4;
|
||||
div->table = cpg_adsp_div_table;
|
||||
div->lock = &cpg->lock;
|
||||
|
||||
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
||||
if (!gate) {
|
||||
kfree(div);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
gate->reg = cpg->reg + CPG_ADSPCKCR;
|
||||
gate->bit_idx = 8;
|
||||
gate->flags = CLK_GATE_SET_TO_DISABLE;
|
||||
gate->lock = &cpg->lock;
|
||||
|
||||
clk = clk_register_composite(NULL, "adsp", &parent_name, 1, NULL, NULL,
|
||||
&div->hw, &clk_divider_ops,
|
||||
&gate->hw, &clk_gate_ops, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(gate);
|
||||
kfree(div);
|
||||
}
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3
|
||||
* 14 13 19 (MHz) *1 *1
|
||||
*---------------------------------------------------
|
||||
* 0 0 0 15 x 1 x172/2 x208/2 x106
|
||||
* 0 0 1 15 x 1 x172/2 x208/2 x88
|
||||
* 0 1 0 20 x 1 x130/2 x156/2 x80
|
||||
* 0 1 1 20 x 1 x130/2 x156/2 x66
|
||||
* 1 0 0 26 / 2 x200/2 x240/2 x122
|
||||
* 1 0 1 26 / 2 x200/2 x240/2 x102
|
||||
* 1 1 0 30 / 2 x172/2 x208/2 x106
|
||||
* 1 1 1 30 / 2 x172/2 x208/2 x88
|
||||
*
|
||||
* *1 : Table 7.6 indicates VCO output (PLLx = VCO/2)
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
|
||||
(((md) & BIT(13)) >> 12) | \
|
||||
(((md) & BIT(19)) >> 19))
|
||||
struct cpg_pll_config {
|
||||
unsigned int extal_div;
|
||||
unsigned int pll1_mult;
|
||||
unsigned int pll3_mult;
|
||||
unsigned int pll0_mult; /* For R-Car V2H and E2 only */
|
||||
};
|
||||
|
||||
static const struct cpg_pll_config cpg_pll_configs[8] __initconst = {
|
||||
{ 1, 208, 106, 200 }, { 1, 208, 88, 200 },
|
||||
{ 1, 156, 80, 150 }, { 1, 156, 66, 150 },
|
||||
{ 2, 240, 122, 230 }, { 2, 240, 102, 230 },
|
||||
{ 2, 208, 106, 200 }, { 2, 208, 88, 200 },
|
||||
};
|
||||
|
||||
/* SDHI divisors */
|
||||
static const struct clk_div_table cpg_sdh_div_table[] = {
|
||||
{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
|
||||
{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
|
||||
{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_div_table cpg_sd01_div_table[] = {
|
||||
{ 4, 8 },
|
||||
{ 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
|
||||
{ 10, 36 }, { 11, 48 }, { 12, 10 }, { 0, 0 },
|
||||
};
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Initialization
|
||||
*/
|
||||
|
||||
static u32 cpg_mode __initdata;
|
||||
|
||||
static const char * const pll0_mult_match[] = {
|
||||
"renesas,r8a7792-cpg-clocks",
|
||||
"renesas,r8a7794-cpg-clocks",
|
||||
NULL
|
||||
};
|
||||
|
||||
static struct clk * __init
|
||||
rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
|
||||
const struct cpg_pll_config *config,
|
||||
const char *name)
|
||||
{
|
||||
const struct clk_div_table *table = NULL;
|
||||
const char *parent_name;
|
||||
unsigned int shift;
|
||||
unsigned int mult = 1;
|
||||
unsigned int div = 1;
|
||||
|
||||
if (!strcmp(name, "main")) {
|
||||
parent_name = of_clk_get_parent_name(np, 0);
|
||||
div = config->extal_div;
|
||||
} else if (!strcmp(name, "pll0")) {
|
||||
/* PLL0 is a configurable multiplier clock. Register it as a
|
||||
* fixed factor clock for now as there's no generic multiplier
|
||||
* clock implementation and we currently have no need to change
|
||||
* the multiplier value.
|
||||
*/
|
||||
if (of_device_compatible_match(np, pll0_mult_match)) {
|
||||
/* R-Car V2H and E2 do not have PLL0CR */
|
||||
mult = config->pll0_mult;
|
||||
div = 3;
|
||||
} else {
|
||||
u32 value = readl(cpg->reg + CPG_PLL0CR);
|
||||
mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
|
||||
}
|
||||
parent_name = "main";
|
||||
} else if (!strcmp(name, "pll1")) {
|
||||
parent_name = "main";
|
||||
mult = config->pll1_mult / 2;
|
||||
} else if (!strcmp(name, "pll3")) {
|
||||
parent_name = "main";
|
||||
mult = config->pll3_mult;
|
||||
} else if (!strcmp(name, "lb")) {
|
||||
parent_name = "pll1";
|
||||
div = cpg_mode & BIT(18) ? 36 : 24;
|
||||
} else if (!strcmp(name, "qspi")) {
|
||||
parent_name = "pll1_div2";
|
||||
div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2)
|
||||
? 8 : 10;
|
||||
} else if (!strcmp(name, "sdh")) {
|
||||
parent_name = "pll1";
|
||||
table = cpg_sdh_div_table;
|
||||
shift = 8;
|
||||
} else if (!strcmp(name, "sd0")) {
|
||||
parent_name = "pll1";
|
||||
table = cpg_sd01_div_table;
|
||||
shift = 4;
|
||||
} else if (!strcmp(name, "sd1")) {
|
||||
parent_name = "pll1";
|
||||
table = cpg_sd01_div_table;
|
||||
shift = 0;
|
||||
} else if (!strcmp(name, "z")) {
|
||||
return cpg_z_clk_register(cpg);
|
||||
} else if (!strcmp(name, "rcan")) {
|
||||
return cpg_rcan_clk_register(cpg, np);
|
||||
} else if (!strcmp(name, "adsp")) {
|
||||
return cpg_adsp_clk_register(cpg);
|
||||
} else {
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
if (!table)
|
||||
return clk_register_fixed_factor(NULL, name, parent_name, 0,
|
||||
mult, div);
|
||||
else
|
||||
return clk_register_divider_table(NULL, name, parent_name, 0,
|
||||
cpg->reg + CPG_SDCKCR, shift,
|
||||
4, 0, table, &cpg->lock);
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset register definitions.
|
||||
*/
|
||||
#define MODEMR 0xe6160060
|
||||
|
||||
static u32 __init rcar_gen2_read_mode_pins(void)
|
||||
{
|
||||
void __iomem *modemr = ioremap_nocache(MODEMR, 4);
|
||||
u32 mode;
|
||||
|
||||
BUG_ON(!modemr);
|
||||
mode = ioread32(modemr);
|
||||
iounmap(modemr);
|
||||
|
||||
return mode;
|
||||
}
|
||||
|
||||
static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
|
||||
{
|
||||
const struct cpg_pll_config *config;
|
||||
struct rcar_gen2_cpg *cpg;
|
||||
struct clk **clks;
|
||||
unsigned int i;
|
||||
int num_clks;
|
||||
|
||||
if (rcar_rst_read_mode_pins(&cpg_mode)) {
|
||||
/* Backward-compatibility with old DT */
|
||||
pr_warn("%pOF: failed to obtain mode pins from RST\n", np);
|
||||
cpg_mode = rcar_gen2_read_mode_pins();
|
||||
}
|
||||
|
||||
num_clks = of_property_count_strings(np, "clock-output-names");
|
||||
if (num_clks < 0) {
|
||||
pr_err("%s: failed to count clocks\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
|
||||
clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
|
||||
if (cpg == NULL || clks == NULL) {
|
||||
/* We're leaking memory on purpose, there's no point in cleaning
|
||||
* up as the system won't boot anyway.
|
||||
*/
|
||||
return;
|
||||
}
|
||||
|
||||
spin_lock_init(&cpg->lock);
|
||||
|
||||
cpg->data.clks = clks;
|
||||
cpg->data.clk_num = num_clks;
|
||||
|
||||
cpg->reg = of_iomap(np, 0);
|
||||
if (WARN_ON(cpg->reg == NULL))
|
||||
return;
|
||||
|
||||
config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
|
||||
for (i = 0; i < num_clks; ++i) {
|
||||
const char *name;
|
||||
struct clk *clk;
|
||||
|
||||
of_property_read_string_index(np, "clock-output-names", i,
|
||||
&name);
|
||||
|
||||
clk = rcar_gen2_cpg_register_clock(np, cpg, config, name);
|
||||
if (IS_ERR(clk))
|
||||
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
|
||||
__func__, np, name, PTR_ERR(clk));
|
||||
else
|
||||
cpg->data.clks[i] = clk;
|
||||
}
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
|
||||
|
||||
cpg_mstp_add_clk_domain(np);
|
||||
}
|
||||
CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
|
||||
rcar_gen2_cpg_clocks_init);
|
||||
|
|
@ -0,0 +1,327 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a774b1 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2019 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on r8a7796-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/soc/renesas/rcar-rst.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A774B1_CLK_CANFD,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL4,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL1_DIV4,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RINT,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_GEN3_Z("z", R8A774B1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
|
||||
DEF_FIXED("ztr", R8A774B1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A774B1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A774B1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED("zx", R8A774B1_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED("s0d1", R8A774B1_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d2", R8A774B1_CLK_S0D2, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3", R8A774B1_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4", R8A774B1_CLK_S0D4, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d6", R8A774B1_CLK_S0D6, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d8", R8A774B1_CLK_S0D8, CLK_S0, 8, 1),
|
||||
DEF_FIXED("s0d12", R8A774B1_CLK_S0D12, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s1d2", R8A774B1_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A774B1_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A774B1_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A774B1_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A774B1_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A774B1_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A774B1_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A774B1_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
|
||||
DEF_FIXED("cl", R8A774B1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A774B1_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A774B1_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A774B1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
DEF_DIV6P1("hdmi", R8A774B1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
|
||||
|
||||
DEF_GEN3_OSC("osc", R8A774B1_CLK_OSC, CLK_EXTAL, 8),
|
||||
|
||||
DEF_BASE("r", R8A774B1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
|
||||
DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6),
|
||||
DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("tmu1", 124, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("tmu0", 125, R8A774B1_CLK_CP),
|
||||
DEF_MOD("fdp1-0", 119, R8A774B1_CLK_S0D1),
|
||||
DEF_MOD("scif5", 202, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("scif3", 204, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("scif1", 206, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("scif0", 207, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("msiof3", 208, R8A774B1_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A774B1_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A774B1_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A774B1_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac1", 218, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac0", 219, R8A774B1_CLK_S0D3),
|
||||
DEF_MOD("cmt3", 300, R8A774B1_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A774B1_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A774B1_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A774B1_CLK_R),
|
||||
DEF_MOD("tpu0", 304, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("scif2", 310, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("sdif3", 311, R8A774B1_CLK_SD3),
|
||||
DEF_MOD("sdif2", 312, R8A774B1_CLK_SD2),
|
||||
DEF_MOD("sdif1", 313, R8A774B1_CLK_SD1),
|
||||
DEF_MOD("sdif0", 314, R8A774B1_CLK_SD0),
|
||||
DEF_MOD("pcie1", 318, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("pcie0", 319, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("usb3-if0", 328, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac0", 330, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac1", 331, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("rwdt", 402, R8A774B1_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A774B1_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A774B1_CLK_S0D3),
|
||||
DEF_MOD("audmac1", 501, R8A774B1_CLK_S1D2),
|
||||
DEF_MOD("audmac0", 502, R8A774B1_CLK_S1D2),
|
||||
DEF_MOD("hscif4", 516, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("hscif3", 517, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("hscif2", 518, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("hscif1", 519, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("hscif0", 520, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("thermal", 522, R8A774B1_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A774B1_CLK_S0D12),
|
||||
DEF_MOD("fcpvd1", 602, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("fcpvd0", 603, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("fcpvb0", 607, R8A774B1_CLK_S0D1),
|
||||
DEF_MOD("fcpvi0", 611, R8A774B1_CLK_S0D1),
|
||||
DEF_MOD("fcpf0", 615, R8A774B1_CLK_S0D1),
|
||||
DEF_MOD("fcpcs", 619, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vspd1", 622, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vspd0", 623, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vspb", 626, R8A774B1_CLK_S0D1),
|
||||
DEF_MOD("vspi0", 631, R8A774B1_CLK_S0D1),
|
||||
DEF_MOD("ehci1", 702, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("ehci0", 703, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("hsusb", 704, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("csi20", 714, R8A774B1_CLK_CSI0),
|
||||
DEF_MOD("csi40", 716, R8A774B1_CLK_CSI0),
|
||||
DEF_MOD("du3", 721, R8A774B1_CLK_S2D1),
|
||||
DEF_MOD("du1", 723, R8A774B1_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A774B1_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A774B1_CLK_S2D1),
|
||||
DEF_MOD("hdmi0", 729, R8A774B1_CLK_HDMI),
|
||||
DEF_MOD("vin7", 804, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vin6", 805, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vin5", 806, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vin4", 807, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vin3", 808, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vin2", 809, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vin1", 810, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vin0", 811, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("etheravb", 812, R8A774B1_CLK_S0D6),
|
||||
DEF_MOD("sata0", 815, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("gpio7", 905, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("gpio6", 906, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("gpio5", 907, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("gpio4", 908, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("gpio3", 909, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("gpio2", 910, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("gpio1", 911, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("gpio0", 912, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("can-fd", 914, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
|
||||
DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A774B1_CLK_S0D6),
|
||||
DEF_MOD("i2c3", 928, R8A774B1_CLK_S0D6),
|
||||
DEF_MOD("i2c2", 929, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("ssi-all", 1005, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
static const unsigned int r8a774b1_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
|
||||
* 14 13 19 17 (MHz)
|
||||
*-----------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16
|
||||
* 0 1 0 0 20 x 1 x150 x160 x160 x120 /19
|
||||
* 0 1 0 1 20 x 1 x150 x160 x106 x120 /19
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x160 x120 /19
|
||||
* 1 0 0 0 25 x 1 x120 x128 x128 x96 /24
|
||||
* 1 0 0 1 25 x 1 x120 x128 x84 x96 /24
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x128 x96 /24
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
(((md) & BIT(19)) >> 18) | \
|
||||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 192, 1, 128, 1, 16, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 160, 1, 106, 1, 19, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 1, 128, 1, 84, 1, 24, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
{ 2, 192, 1, 128, 1, 32, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
static int __init r8a774b1_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
|
||||
u32 cpg_mode;
|
||||
int error;
|
||||
|
||||
error = rcar_rst_read_mode_pins(&cpg_mode);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
if (!cpg_pll_config->extal_div) {
|
||||
dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a774b1_cpg_mssr_info __initconst = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r8a774b1_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r8a774b1_core_clks),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r8a774b1_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r8a774b1_mod_clks),
|
||||
.num_hw_mod_clks = 12 * 32,
|
||||
|
||||
/* Critical Module Clocks */
|
||||
.crit_mod_clks = r8a774b1_crit_mod_clks,
|
||||
.num_crit_mod_clks = ARRAY_SIZE(r8a774b1_crit_mod_clks),
|
||||
|
||||
/* Callbacks */
|
||||
.init = r8a774b1_cpg_mssr_init,
|
||||
.cpg_clk_register = rcar_gen3_cpg_clk_register,
|
||||
};
|
||||
|
|
@ -1,9 +1,10 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
* r8a7796 (R-Car M3-W/W+) Clock Pulse Generator / Module Standby and Software
|
||||
* Reset
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
* Copyright (C) 2016-2019 Glider bvba
|
||||
* Copyright (C) 2018-2019 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
|
|
@ -14,6 +15,7 @@
|
|||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/soc/renesas/rcar-rst.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
|
||||
|
|
@ -116,7 +118,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
|
|||
DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
|
||||
static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
|
||||
DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
|
||||
DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
|
||||
|
|
@ -304,6 +306,14 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
|
|||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
/*
|
||||
* Fixups for R-Car M3-W+
|
||||
*/
|
||||
|
||||
static const unsigned int r8a77961_mod_nullify[] __initconst = {
|
||||
MOD_CLK_ID(617), /* FCPCI0 */
|
||||
};
|
||||
|
||||
static int __init r8a7796_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
|
||||
|
|
@ -320,6 +330,12 @@ static int __init r8a7796_cpg_mssr_init(struct device *dev)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (of_device_is_compatible(dev->of_node, "renesas,r8a77961-cpg-mssr"))
|
||||
mssr_mod_nullify(r8a7796_mod_clks,
|
||||
ARRAY_SIZE(r8a7796_mod_clks),
|
||||
r8a77961_mod_nullify,
|
||||
ARRAY_SIZE(r8a77961_mod_nullify));
|
||||
|
||||
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -323,7 +323,7 @@ static int __init r8a77965_cpg_mssr_init(struct device *dev)
|
|||
}
|
||||
|
||||
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
|
||||
};
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a77965_cpg_mssr_info __initconst = {
|
||||
/* Core Clocks */
|
||||
|
|
|
|||
|
|
@ -63,19 +63,22 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
|
|||
return div_u64((u64)parent_rate * mult, 32);
|
||||
}
|
||||
|
||||
static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
static int cpg_z_clk_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
unsigned long prate = *parent_rate;
|
||||
unsigned int mult;
|
||||
unsigned long prate = req->best_parent_rate;
|
||||
unsigned int min_mult, max_mult, mult;
|
||||
|
||||
if (!prate)
|
||||
prate = 1;
|
||||
min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
|
||||
max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
|
||||
if (max_mult < min_mult)
|
||||
return -EINVAL;
|
||||
|
||||
mult = div_u64((u64)rate * 32, prate);
|
||||
mult = clamp(mult, 1U, 32U);
|
||||
mult = div64_ul(req->rate * 32ULL, prate);
|
||||
mult = clamp(mult, min_mult, max_mult);
|
||||
|
||||
return *parent_rate / 32 * mult;
|
||||
req->rate = div_u64((u64)prate * mult, 32);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
|
@ -86,7 +89,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
u32 val, kick;
|
||||
unsigned int i;
|
||||
|
||||
mult = div_u64((u64)rate * 32, parent_rate);
|
||||
mult = div64_ul(rate * 32ULL, parent_rate);
|
||||
mult = clamp(mult, 1U, 32U);
|
||||
|
||||
if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
|
||||
|
|
@ -126,7 +129,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
|
||||
static const struct clk_ops cpg_z_clk_ops = {
|
||||
.recalc_rate = cpg_z_clk_recalc_rate,
|
||||
.round_rate = cpg_z_clk_round_rate,
|
||||
.determine_rate = cpg_z_clk_determine_rate,
|
||||
.set_rate = cpg_z_clk_set_rate,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -114,18 +114,24 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
|
|||
32 * zclk->fixed_div);
|
||||
}
|
||||
|
||||
static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
static int cpg_z_clk_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct cpg_z_clk *zclk = to_z_clk(hw);
|
||||
unsigned int min_mult, max_mult, mult;
|
||||
unsigned long prate;
|
||||
unsigned int mult;
|
||||
|
||||
prate = *parent_rate / zclk->fixed_div;
|
||||
mult = div_u64(rate * 32ULL, prate);
|
||||
mult = clamp(mult, 1U, 32U);
|
||||
prate = req->best_parent_rate / zclk->fixed_div;
|
||||
min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
|
||||
max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
|
||||
if (max_mult < min_mult)
|
||||
return -EINVAL;
|
||||
|
||||
return (u64)prate * mult / 32;
|
||||
mult = div64_ul(req->rate * 32ULL, prate);
|
||||
mult = clamp(mult, min_mult, max_mult);
|
||||
|
||||
req->rate = div_u64((u64)prate * mult, 32);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
|
@ -172,7 +178,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
|
||||
static const struct clk_ops cpg_z_clk_ops = {
|
||||
.recalc_rate = cpg_z_clk_recalc_rate,
|
||||
.round_rate = cpg_z_clk_round_rate,
|
||||
.determine_rate = cpg_z_clk_determine_rate,
|
||||
.set_rate = cpg_z_clk_set_rate,
|
||||
};
|
||||
|
||||
|
|
@ -309,44 +315,44 @@ static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
|
|||
clock->div_table[clock->cur_div_idx].div);
|
||||
}
|
||||
|
||||
static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
|
||||
unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
static int cpg_sd_clock_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
unsigned long calc_rate, diff, diff_min = ULONG_MAX;
|
||||
unsigned int i, best_div = 0;
|
||||
unsigned long best_rate = ULONG_MAX, diff_min = ULONG_MAX;
|
||||
struct sd_clock *clock = to_sd_clock(hw);
|
||||
unsigned long calc_rate, diff;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < clock->div_num; i++) {
|
||||
calc_rate = DIV_ROUND_CLOSEST(parent_rate,
|
||||
calc_rate = DIV_ROUND_CLOSEST(req->best_parent_rate,
|
||||
clock->div_table[i].div);
|
||||
diff = calc_rate > rate ? calc_rate - rate : rate - calc_rate;
|
||||
if (calc_rate < req->min_rate || calc_rate > req->max_rate)
|
||||
continue;
|
||||
|
||||
diff = calc_rate > req->rate ? calc_rate - req->rate
|
||||
: req->rate - calc_rate;
|
||||
if (diff < diff_min) {
|
||||
best_div = clock->div_table[i].div;
|
||||
best_rate = calc_rate;
|
||||
diff_min = diff;
|
||||
}
|
||||
}
|
||||
|
||||
return best_div;
|
||||
}
|
||||
if (best_rate == ULONG_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
struct sd_clock *clock = to_sd_clock(hw);
|
||||
unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
|
||||
|
||||
return DIV_ROUND_CLOSEST(*parent_rate, div);
|
||||
req->rate = best_rate;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct sd_clock *clock = to_sd_clock(hw);
|
||||
unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < clock->div_num; i++)
|
||||
if (div == clock->div_table[i].div)
|
||||
if (rate == DIV_ROUND_CLOSEST(parent_rate,
|
||||
clock->div_table[i].div))
|
||||
break;
|
||||
|
||||
if (i >= clock->div_num)
|
||||
|
|
@ -366,7 +372,7 @@ static const struct clk_ops cpg_sd_clock_ops = {
|
|||
.disable = cpg_sd_clock_disable,
|
||||
.is_enabled = cpg_sd_clock_is_enabled,
|
||||
.recalc_rate = cpg_sd_clock_recalc_rate,
|
||||
.round_rate = cpg_sd_clock_round_rate,
|
||||
.determine_rate = cpg_sd_clock_determine_rate,
|
||||
.set_rate = cpg_sd_clock_set_rate,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -702,6 +702,12 @@ static const struct of_device_id cpg_mssr_match[] = {
|
|||
.data = &r8a774a1_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A774B1
|
||||
{
|
||||
.compatible = "renesas,r8a774b1-cpg-mssr",
|
||||
.data = &r8a774b1_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A774C0
|
||||
{
|
||||
.compatible = "renesas,r8a774c0-cpg-mssr",
|
||||
|
|
@ -743,12 +749,18 @@ static const struct of_device_id cpg_mssr_match[] = {
|
|||
.data = &r8a7795_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A7796
|
||||
#ifdef CONFIG_CLK_R8A77960
|
||||
{
|
||||
.compatible = "renesas,r8a7796-cpg-mssr",
|
||||
.data = &r8a7796_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A77961
|
||||
{
|
||||
.compatible = "renesas,r8a77961-cpg-mssr",
|
||||
.data = &r8a7796_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A77965
|
||||
{
|
||||
.compatible = "renesas,r8a77965-cpg-mssr",
|
||||
|
|
|
|||
|
|
@ -159,6 +159,7 @@ extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
|
|||
extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a774a1_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a774b1_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a774c0_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,57 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2019 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a774b1 CPG Core Clocks */
|
||||
#define R8A774B1_CLK_Z 0
|
||||
#define R8A774B1_CLK_ZG 1
|
||||
#define R8A774B1_CLK_ZTR 2
|
||||
#define R8A774B1_CLK_ZTRD2 3
|
||||
#define R8A774B1_CLK_ZT 4
|
||||
#define R8A774B1_CLK_ZX 5
|
||||
#define R8A774B1_CLK_S0D1 6
|
||||
#define R8A774B1_CLK_S0D2 7
|
||||
#define R8A774B1_CLK_S0D3 8
|
||||
#define R8A774B1_CLK_S0D4 9
|
||||
#define R8A774B1_CLK_S0D6 10
|
||||
#define R8A774B1_CLK_S0D8 11
|
||||
#define R8A774B1_CLK_S0D12 12
|
||||
#define R8A774B1_CLK_S1D2 13
|
||||
#define R8A774B1_CLK_S1D4 14
|
||||
#define R8A774B1_CLK_S2D1 15
|
||||
#define R8A774B1_CLK_S2D2 16
|
||||
#define R8A774B1_CLK_S2D4 17
|
||||
#define R8A774B1_CLK_S3D1 18
|
||||
#define R8A774B1_CLK_S3D2 19
|
||||
#define R8A774B1_CLK_S3D4 20
|
||||
#define R8A774B1_CLK_LB 21
|
||||
#define R8A774B1_CLK_CL 22
|
||||
#define R8A774B1_CLK_ZB3 23
|
||||
#define R8A774B1_CLK_ZB3D2 24
|
||||
#define R8A774B1_CLK_CR 25
|
||||
#define R8A774B1_CLK_DDR 26
|
||||
#define R8A774B1_CLK_SD0H 27
|
||||
#define R8A774B1_CLK_SD0 28
|
||||
#define R8A774B1_CLK_SD1H 29
|
||||
#define R8A774B1_CLK_SD1 30
|
||||
#define R8A774B1_CLK_SD2H 31
|
||||
#define R8A774B1_CLK_SD2 32
|
||||
#define R8A774B1_CLK_SD3H 33
|
||||
#define R8A774B1_CLK_SD3 34
|
||||
#define R8A774B1_CLK_RPC 35
|
||||
#define R8A774B1_CLK_RPCD2 36
|
||||
#define R8A774B1_CLK_MSO 37
|
||||
#define R8A774B1_CLK_HDMI 38
|
||||
#define R8A774B1_CLK_CSI0 39
|
||||
#define R8A774B1_CLK_CP 40
|
||||
#define R8A774B1_CLK_CPEX 41
|
||||
#define R8A774B1_CLK_R 42
|
||||
#define R8A774B1_CLK_OSC 43
|
||||
#define R8A774B1_CLK_CANFD 44
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Copyright (C) 2019 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a77961 CPG Core Clocks */
|
||||
#define R8A77961_CLK_Z 0
|
||||
#define R8A77961_CLK_Z2 1
|
||||
#define R8A77961_CLK_ZR 2
|
||||
#define R8A77961_CLK_ZG 3
|
||||
#define R8A77961_CLK_ZTR 4
|
||||
#define R8A77961_CLK_ZTRD2 5
|
||||
#define R8A77961_CLK_ZT 6
|
||||
#define R8A77961_CLK_ZX 7
|
||||
#define R8A77961_CLK_S0D1 8
|
||||
#define R8A77961_CLK_S0D2 9
|
||||
#define R8A77961_CLK_S0D3 10
|
||||
#define R8A77961_CLK_S0D4 11
|
||||
#define R8A77961_CLK_S0D6 12
|
||||
#define R8A77961_CLK_S0D8 13
|
||||
#define R8A77961_CLK_S0D12 14
|
||||
#define R8A77961_CLK_S1D1 15
|
||||
#define R8A77961_CLK_S1D2 16
|
||||
#define R8A77961_CLK_S1D4 17
|
||||
#define R8A77961_CLK_S2D1 18
|
||||
#define R8A77961_CLK_S2D2 19
|
||||
#define R8A77961_CLK_S2D4 20
|
||||
#define R8A77961_CLK_S3D1 21
|
||||
#define R8A77961_CLK_S3D2 22
|
||||
#define R8A77961_CLK_S3D4 23
|
||||
#define R8A77961_CLK_LB 24
|
||||
#define R8A77961_CLK_CL 25
|
||||
#define R8A77961_CLK_ZB3 26
|
||||
#define R8A77961_CLK_ZB3D2 27
|
||||
#define R8A77961_CLK_ZB3D4 28
|
||||
#define R8A77961_CLK_CR 29
|
||||
#define R8A77961_CLK_CRD2 30
|
||||
#define R8A77961_CLK_SD0H 31
|
||||
#define R8A77961_CLK_SD0 32
|
||||
#define R8A77961_CLK_SD1H 33
|
||||
#define R8A77961_CLK_SD1 34
|
||||
#define R8A77961_CLK_SD2H 35
|
||||
#define R8A77961_CLK_SD2 36
|
||||
#define R8A77961_CLK_SD3H 37
|
||||
#define R8A77961_CLK_SD3 38
|
||||
#define R8A77961_CLK_SSP2 39
|
||||
#define R8A77961_CLK_SSP1 40
|
||||
#define R8A77961_CLK_SSPRS 41
|
||||
#define R8A77961_CLK_RPC 42
|
||||
#define R8A77961_CLK_RPCD2 43
|
||||
#define R8A77961_CLK_MSO 44
|
||||
#define R8A77961_CLK_CANFD 45
|
||||
#define R8A77961_CLK_HDMI 46
|
||||
#define R8A77961_CLK_CSI0 47
|
||||
/* CLK_CSIREF was removed */
|
||||
#define R8A77961_CLK_CP 49
|
||||
#define R8A77961_CLK_CPEX 50
|
||||
#define R8A77961_CLK_R 51
|
||||
#define R8A77961_CLK_OSC 52
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2019 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A774B1_PD_CA57_CPU0 0
|
||||
#define R8A774B1_PD_CA57_CPU1 1
|
||||
#define R8A774B1_PD_A3VP 9
|
||||
#define R8A774B1_PD_CA57_SCU 12
|
||||
#define R8A774B1_PD_A3VC 14
|
||||
#define R8A774B1_PD_3DG_A 17
|
||||
#define R8A774B1_PD_3DG_B 18
|
||||
#define R8A774B1_PD_A2VC1 26
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A774B1_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ */
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2019 Glider bvba
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A77961_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A77961_PD_CA57_CPU0 0
|
||||
#define R8A77961_PD_CA57_CPU1 1
|
||||
#define R8A77961_PD_CA53_CPU0 5
|
||||
#define R8A77961_PD_CA53_CPU1 6
|
||||
#define R8A77961_PD_CA53_CPU2 7
|
||||
#define R8A77961_PD_CA53_CPU3 8
|
||||
#define R8A77961_PD_CA57_SCU 12
|
||||
#define R8A77961_PD_CR7 13
|
||||
#define R8A77961_PD_A3VC 14
|
||||
#define R8A77961_PD_3DG_A 17
|
||||
#define R8A77961_PD_3DG_B 18
|
||||
#define R8A77961_PD_CA53_SCU 21
|
||||
#define R8A77961_PD_A3IR 24
|
||||
#define R8A77961_PD_A2VC1 26
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A77961_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */
|
||||
Loading…
Reference in New Issue