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arm64: remove unnecessary cache flush at boot 

Currently we flush the entire dcache at boot within __cpu_setup, but
this is unnecessary as the booting protocol demands that the dcache is
invalid and off upon entering the kernel. The presence of the cache
flush only serves to hide bugs in bootloaders, and is not safe in the
presence of SMP.

In an SMP boot scenario the CPUs enter coherency outside of the kernel,
and the primary CPU enables its caches before bringing up secondary
CPUs. Therefore if any secondary CPU has an entry in its cache (in
violation of the boot protocol), the primary CPU might snoop it even if
the secondary CPU's cache is disabled. The boot-time cache flush only
serves to hide a firmware bug, and slows down a cpu boot unnecessarily.

This patch removes the unnecessary boot-time cache flush.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
[catalin.marinas@arm.com: make __flush_dcache_all local only]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Mark Rutland 2013-08-14 09:54:54 +01:00 committed by Catalin Marinas
parent addea9ef05
commit bff705950e
2 changed files with 1 additions and 7 deletions
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2
arch/arm64/mm/cache.S
View File

@ -30,7 +30,7 @@
* *
* Corrupted registers: x0-x7, x9-x11 * Corrupted registers: x0-x7, x9-x11
*/ */
ENTRY(__flush_dcache_all) __flush_dcache_all:
dsb sy // ensure ordering with previous memory accesses dsb sy // ensure ordering with previous memory accesses
mrs x0, clidr_el1 // read clidr mrs x0, clidr_el1 // read clidr
and x3, x0, #0x7000000 // extract loc from clidr and x3, x0, #0x7000000 // extract loc from clidr

6
arch/arm64/mm/proc.S
View File

@ -173,12 +173,6 @@ ENDPROC(cpu_do_switch_mm)
* value of the SCTLR_EL1 register. * value of the SCTLR_EL1 register.
*/ */
ENTRY(__cpu_setup) ENTRY(__cpu_setup)
/*
* Preserve the link register across the function call.
*/
mov x28, lr
bl __flush_dcache_all
mov lr, x28
ic iallu // I+BTB cache invalidate ic iallu // I+BTB cache invalidate
tlbi vmalle1is // invalidate I + D TLBs tlbi vmalle1is // invalidate I + D TLBs
dsb sy dsb sy