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perf/x86/intel: Don't disable "intel_bts" around "intel" event batching 

At the moment, intel_bts events get disabled from intel PMU's disable
callback, which includes event scheduling transactions of said PMU,
which have nothing to do with intel_bts events.

We do want to keep intel_bts events off inside the PMI handler to
avoid filling up their buffer too soon.

This patch moves intel_bts enabling/disabling directly to the PMI
handler.

Reported-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: vince@deater.net
Link: http://lkml.kernel.org/r/20160915082233.11065-1-alexander.shishkin@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Alexander Shishkin 2016-09-15 11:22:33 +03:00 committed by Ingo Molnar
parent 4cea877657
commit cecf62352a
1 changed files with 8 additions and 7 deletions
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15
arch/x86/events/intel/core.c
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@ -1730,9 +1730,11 @@ static __initconst const u64 knl_hw_cache_extra_regs
* disabled state if called consecutively. * disabled state if called consecutively.
* *
* During consecutive calls, the same disable value will be written to related * During consecutive calls, the same disable value will be written to related
* registers, so the PMU state remains unchanged. hw.state in * registers, so the PMU state remains unchanged.
* intel_bts_disable_local will remain PERF_HES_STOPPED too in consecutive *
* calls. * intel_bts events don't coexist with intel PMU's BTS events because of
* x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
* disabled around intel PMU's event batching etc, only inside the PMI handler.
*/ */
static void __intel_pmu_disable_all(void) static void __intel_pmu_disable_all(void)
{ {
@ -1742,8 +1744,6 @@ static void __intel_pmu_disable_all(void)
if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
intel_pmu_disable_bts(); intel_pmu_disable_bts();
else
intel_bts_disable_local();
intel_pmu_pebs_disable_all(); intel_pmu_pebs_disable_all();
} }
@ -1771,8 +1771,7 @@ static void __intel_pmu_enable_all(int added, bool pmi)
return; return;
intel_pmu_enable_bts(event->hw.config); intel_pmu_enable_bts(event->hw.config);
} else }
intel_bts_enable_local();
} }
static void intel_pmu_enable_all(int added) static void intel_pmu_enable_all(int added)
@ -2073,6 +2072,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
*/ */
if (!x86_pmu.late_ack) if (!x86_pmu.late_ack)
apic_write(APIC_LVTPC, APIC_DM_NMI); apic_write(APIC_LVTPC, APIC_DM_NMI);
intel_bts_disable_local();
__intel_pmu_disable_all(); __intel_pmu_disable_all();
handled = intel_pmu_drain_bts_buffer(); handled = intel_pmu_drain_bts_buffer();
handled += intel_bts_interrupt(); handled += intel_bts_interrupt();
@ -2172,6 +2172,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
/* Only restore PMU state when it's active. See x86_pmu_disable(). */ /* Only restore PMU state when it's active. See x86_pmu_disable(). */
if (cpuc->enabled) if (cpuc->enabled)
__intel_pmu_enable_all(0, true); __intel_pmu_enable_all(0, true);
intel_bts_enable_local();
/* /*
* Only unmask the NMI after the overflow counters * Only unmask the NMI after the overflow counters