KVM: arm64: re-factor hyp.S debug register code
This is a pre-cursor to sharing the code with the guest debug support. This replaces the big macro that fishes data out of a fixed location with a more general helper macro to restore a set of debug registers. It uses macro substitution so it can be re-used for debug control and value registers. It does however rely on the debug registers being 64 bit aligned (as they happen to be in the hyp ABI). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Alex Bennée
Marc Zyngier
parent
337b99bf7e
commit
e0a1b9a937
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@ -230,199 +230,52 @@
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stp x24, x25, [x3, #160]
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.endm
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.macro save_debug
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// x2: base address for cpu context
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// x3: tmp register
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.macro save_debug type
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// x4: pointer to register set
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// x5: number of registers to skip
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// x6..x22 trashed
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mrs x26, id_aa64dfr0_el1
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ubfx x24, x26, #12, #4 // Extract BRPs
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ubfx x25, x26, #20, #4 // Extract WRPs
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mov w26, #15
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sub w24, w26, w24 // How many BPs to skip
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sub w25, w26, w25 // How many WPs to skip
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add x3, x2, #CPU_SYSREG_OFFSET(DBGBCR0_EL1)
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adr x26, 1f
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add x26, x26, x24, lsl #2
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br x26
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adr x22, 1f
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add x22, x22, x5, lsl #2
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br x22
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1:
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mrs x20, dbgbcr15_el1
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mrs x19, dbgbcr14_el1
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mrs x18, dbgbcr13_el1
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mrs x17, dbgbcr12_el1
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mrs x16, dbgbcr11_el1
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mrs x15, dbgbcr10_el1
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mrs x14, dbgbcr9_el1
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mrs x13, dbgbcr8_el1
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mrs x12, dbgbcr7_el1
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mrs x11, dbgbcr6_el1
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mrs x10, dbgbcr5_el1
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mrs x9, dbgbcr4_el1
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mrs x8, dbgbcr3_el1
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mrs x7, dbgbcr2_el1
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mrs x6, dbgbcr1_el1
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mrs x5, dbgbcr0_el1
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adr x26, 1f
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add x26, x26, x24, lsl #2
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br x26
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mrs x21, \type\()15_el1
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mrs x20, \type\()14_el1
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mrs x19, \type\()13_el1
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mrs x18, \type\()12_el1
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mrs x17, \type\()11_el1
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mrs x16, \type\()10_el1
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mrs x15, \type\()9_el1
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mrs x14, \type\()8_el1
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mrs x13, \type\()7_el1
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mrs x12, \type\()6_el1
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mrs x11, \type\()5_el1
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mrs x10, \type\()4_el1
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mrs x9, \type\()3_el1
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mrs x8, \type\()2_el1
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mrs x7, \type\()1_el1
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mrs x6, \type\()0_el1
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adr x22, 1f
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add x22, x22, x5, lsl #2
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br x22
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1:
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str x20, [x3, #(15 * 8)]
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str x19, [x3, #(14 * 8)]
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str x18, [x3, #(13 * 8)]
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str x17, [x3, #(12 * 8)]
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str x16, [x3, #(11 * 8)]
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str x15, [x3, #(10 * 8)]
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str x14, [x3, #(9 * 8)]
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str x13, [x3, #(8 * 8)]
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str x12, [x3, #(7 * 8)]
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str x11, [x3, #(6 * 8)]
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str x10, [x3, #(5 * 8)]
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str x9, [x3, #(4 * 8)]
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str x8, [x3, #(3 * 8)]
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str x7, [x3, #(2 * 8)]
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str x6, [x3, #(1 * 8)]
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str x5, [x3, #(0 * 8)]
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add x3, x2, #CPU_SYSREG_OFFSET(DBGBVR0_EL1)
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adr x26, 1f
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add x26, x26, x24, lsl #2
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br x26
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1:
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mrs x20, dbgbvr15_el1
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mrs x19, dbgbvr14_el1
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mrs x18, dbgbvr13_el1
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mrs x17, dbgbvr12_el1
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mrs x16, dbgbvr11_el1
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mrs x15, dbgbvr10_el1
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mrs x14, dbgbvr9_el1
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mrs x13, dbgbvr8_el1
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mrs x12, dbgbvr7_el1
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mrs x11, dbgbvr6_el1
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mrs x10, dbgbvr5_el1
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mrs x9, dbgbvr4_el1
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mrs x8, dbgbvr3_el1
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mrs x7, dbgbvr2_el1
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mrs x6, dbgbvr1_el1
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mrs x5, dbgbvr0_el1
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adr x26, 1f
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add x26, x26, x24, lsl #2
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br x26
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1:
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str x20, [x3, #(15 * 8)]
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str x19, [x3, #(14 * 8)]
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str x18, [x3, #(13 * 8)]
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str x17, [x3, #(12 * 8)]
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str x16, [x3, #(11 * 8)]
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str x15, [x3, #(10 * 8)]
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str x14, [x3, #(9 * 8)]
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str x13, [x3, #(8 * 8)]
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str x12, [x3, #(7 * 8)]
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str x11, [x3, #(6 * 8)]
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str x10, [x3, #(5 * 8)]
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str x9, [x3, #(4 * 8)]
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str x8, [x3, #(3 * 8)]
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str x7, [x3, #(2 * 8)]
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str x6, [x3, #(1 * 8)]
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str x5, [x3, #(0 * 8)]
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add x3, x2, #CPU_SYSREG_OFFSET(DBGWCR0_EL1)
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adr x26, 1f
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add x26, x26, x25, lsl #2
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br x26
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1:
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mrs x20, dbgwcr15_el1
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mrs x19, dbgwcr14_el1
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mrs x18, dbgwcr13_el1
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mrs x17, dbgwcr12_el1
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mrs x16, dbgwcr11_el1
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mrs x15, dbgwcr10_el1
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mrs x14, dbgwcr9_el1
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mrs x13, dbgwcr8_el1
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mrs x12, dbgwcr7_el1
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mrs x11, dbgwcr6_el1
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mrs x10, dbgwcr5_el1
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mrs x9, dbgwcr4_el1
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mrs x8, dbgwcr3_el1
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mrs x7, dbgwcr2_el1
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mrs x6, dbgwcr1_el1
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mrs x5, dbgwcr0_el1
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adr x26, 1f
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add x26, x26, x25, lsl #2
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br x26
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1:
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str x20, [x3, #(15 * 8)]
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str x19, [x3, #(14 * 8)]
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str x18, [x3, #(13 * 8)]
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str x17, [x3, #(12 * 8)]
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str x16, [x3, #(11 * 8)]
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str x15, [x3, #(10 * 8)]
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str x14, [x3, #(9 * 8)]
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str x13, [x3, #(8 * 8)]
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str x12, [x3, #(7 * 8)]
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str x11, [x3, #(6 * 8)]
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str x10, [x3, #(5 * 8)]
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str x9, [x3, #(4 * 8)]
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str x8, [x3, #(3 * 8)]
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str x7, [x3, #(2 * 8)]
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str x6, [x3, #(1 * 8)]
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str x5, [x3, #(0 * 8)]
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add x3, x2, #CPU_SYSREG_OFFSET(DBGWVR0_EL1)
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adr x26, 1f
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add x26, x26, x25, lsl #2
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br x26
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1:
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mrs x20, dbgwvr15_el1
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mrs x19, dbgwvr14_el1
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mrs x18, dbgwvr13_el1
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mrs x17, dbgwvr12_el1
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mrs x16, dbgwvr11_el1
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mrs x15, dbgwvr10_el1
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mrs x14, dbgwvr9_el1
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mrs x13, dbgwvr8_el1
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mrs x12, dbgwvr7_el1
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mrs x11, dbgwvr6_el1
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mrs x10, dbgwvr5_el1
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mrs x9, dbgwvr4_el1
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mrs x8, dbgwvr3_el1
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mrs x7, dbgwvr2_el1
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mrs x6, dbgwvr1_el1
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mrs x5, dbgwvr0_el1
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adr x26, 1f
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add x26, x26, x25, lsl #2
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br x26
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1:
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str x20, [x3, #(15 * 8)]
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str x19, [x3, #(14 * 8)]
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str x18, [x3, #(13 * 8)]
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str x17, [x3, #(12 * 8)]
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str x16, [x3, #(11 * 8)]
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str x15, [x3, #(10 * 8)]
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str x14, [x3, #(9 * 8)]
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str x13, [x3, #(8 * 8)]
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str x12, [x3, #(7 * 8)]
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str x11, [x3, #(6 * 8)]
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str x10, [x3, #(5 * 8)]
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str x9, [x3, #(4 * 8)]
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str x8, [x3, #(3 * 8)]
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str x7, [x3, #(2 * 8)]
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str x6, [x3, #(1 * 8)]
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str x5, [x3, #(0 * 8)]
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mrs x21, mdccint_el1
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str x21, [x2, #CPU_SYSREG_OFFSET(MDCCINT_EL1)]
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str x21, [x4, #(15 * 8)]
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str x20, [x4, #(14 * 8)]
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str x19, [x4, #(13 * 8)]
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str x18, [x4, #(12 * 8)]
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str x17, [x4, #(11 * 8)]
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str x16, [x4, #(10 * 8)]
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str x15, [x4, #(9 * 8)]
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str x14, [x4, #(8 * 8)]
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str x13, [x4, #(7 * 8)]
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str x12, [x4, #(6 * 8)]
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str x11, [x4, #(5 * 8)]
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str x10, [x4, #(4 * 8)]
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str x9, [x4, #(3 * 8)]
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str x8, [x4, #(2 * 8)]
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str x7, [x4, #(1 * 8)]
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str x6, [x4, #(0 * 8)]
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.endm
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.macro restore_sysregs
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@ -467,195 +320,52 @@
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msr mdscr_el1, x25
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.endm
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.macro restore_debug
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// x2: base address for cpu context
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// x3: tmp register
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.macro restore_debug type
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// x4: pointer to register set
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// x5: number of registers to skip
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// x6..x22 trashed
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mrs x26, id_aa64dfr0_el1
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ubfx x24, x26, #12, #4 // Extract BRPs
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ubfx x25, x26, #20, #4 // Extract WRPs
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mov w26, #15
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sub w24, w26, w24 // How many BPs to skip
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sub w25, w26, w25 // How many WPs to skip
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add x3, x2, #CPU_SYSREG_OFFSET(DBGBCR0_EL1)
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adr x26, 1f
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add x26, x26, x24, lsl #2
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br x26
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adr x22, 1f
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add x22, x22, x5, lsl #2
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br x22
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1:
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ldr x20, [x3, #(15 * 8)]
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ldr x19, [x3, #(14 * 8)]
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ldr x18, [x3, #(13 * 8)]
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ldr x17, [x3, #(12 * 8)]
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ldr x16, [x3, #(11 * 8)]
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ldr x15, [x3, #(10 * 8)]
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ldr x14, [x3, #(9 * 8)]
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ldr x13, [x3, #(8 * 8)]
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ldr x12, [x3, #(7 * 8)]
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ldr x11, [x3, #(6 * 8)]
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ldr x10, [x3, #(5 * 8)]
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ldr x9, [x3, #(4 * 8)]
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ldr x8, [x3, #(3 * 8)]
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ldr x7, [x3, #(2 * 8)]
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ldr x6, [x3, #(1 * 8)]
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ldr x5, [x3, #(0 * 8)]
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ldr x21, [x4, #(15 * 8)]
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ldr x20, [x4, #(14 * 8)]
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ldr x19, [x4, #(13 * 8)]
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ldr x18, [x4, #(12 * 8)]
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ldr x17, [x4, #(11 * 8)]
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ldr x16, [x4, #(10 * 8)]
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ldr x15, [x4, #(9 * 8)]
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ldr x14, [x4, #(8 * 8)]
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ldr x13, [x4, #(7 * 8)]
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ldr x12, [x4, #(6 * 8)]
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ldr x11, [x4, #(5 * 8)]
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ldr x10, [x4, #(4 * 8)]
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ldr x9, [x4, #(3 * 8)]
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ldr x8, [x4, #(2 * 8)]
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ldr x7, [x4, #(1 * 8)]
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ldr x6, [x4, #(0 * 8)]
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adr x26, 1f
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add x26, x26, x24, lsl #2
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br x26
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adr x22, 1f
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add x22, x22, x5, lsl #2
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br x22
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1:
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msr dbgbcr15_el1, x20
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msr dbgbcr14_el1, x19
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msr dbgbcr13_el1, x18
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msr dbgbcr12_el1, x17
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msr dbgbcr11_el1, x16
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msr dbgbcr10_el1, x15
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msr dbgbcr9_el1, x14
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msr dbgbcr8_el1, x13
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msr dbgbcr7_el1, x12
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msr dbgbcr6_el1, x11
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msr dbgbcr5_el1, x10
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msr dbgbcr4_el1, x9
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msr dbgbcr3_el1, x8
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msr dbgbcr2_el1, x7
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msr dbgbcr1_el1, x6
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msr dbgbcr0_el1, x5
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add x3, x2, #CPU_SYSREG_OFFSET(DBGBVR0_EL1)
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adr x26, 1f
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add x26, x26, x24, lsl #2
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br x26
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1:
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ldr x20, [x3, #(15 * 8)]
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ldr x19, [x3, #(14 * 8)]
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ldr x18, [x3, #(13 * 8)]
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ldr x17, [x3, #(12 * 8)]
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ldr x16, [x3, #(11 * 8)]
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ldr x15, [x3, #(10 * 8)]
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ldr x14, [x3, #(9 * 8)]
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ldr x13, [x3, #(8 * 8)]
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ldr x12, [x3, #(7 * 8)]
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ldr x11, [x3, #(6 * 8)]
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ldr x10, [x3, #(5 * 8)]
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ldr x9, [x3, #(4 * 8)]
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ldr x8, [x3, #(3 * 8)]
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ldr x7, [x3, #(2 * 8)]
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ldr x6, [x3, #(1 * 8)]
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ldr x5, [x3, #(0 * 8)]
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adr x26, 1f
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add x26, x26, x24, lsl #2
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br x26
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1:
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msr dbgbvr15_el1, x20
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msr dbgbvr14_el1, x19
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msr dbgbvr13_el1, x18
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msr dbgbvr12_el1, x17
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msr dbgbvr11_el1, x16
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msr dbgbvr10_el1, x15
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msr dbgbvr9_el1, x14
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msr dbgbvr8_el1, x13
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msr dbgbvr7_el1, x12
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msr dbgbvr6_el1, x11
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msr dbgbvr5_el1, x10
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msr dbgbvr4_el1, x9
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msr dbgbvr3_el1, x8
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msr dbgbvr2_el1, x7
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msr dbgbvr1_el1, x6
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msr dbgbvr0_el1, x5
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add x3, x2, #CPU_SYSREG_OFFSET(DBGWCR0_EL1)
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adr x26, 1f
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add x26, x26, x25, lsl #2
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br x26
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1:
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ldr x20, [x3, #(15 * 8)]
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ldr x19, [x3, #(14 * 8)]
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ldr x18, [x3, #(13 * 8)]
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ldr x17, [x3, #(12 * 8)]
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ldr x16, [x3, #(11 * 8)]
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ldr x15, [x3, #(10 * 8)]
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ldr x14, [x3, #(9 * 8)]
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ldr x13, [x3, #(8 * 8)]
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ldr x12, [x3, #(7 * 8)]
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ldr x11, [x3, #(6 * 8)]
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ldr x10, [x3, #(5 * 8)]
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ldr x9, [x3, #(4 * 8)]
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ldr x8, [x3, #(3 * 8)]
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ldr x7, [x3, #(2 * 8)]
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ldr x6, [x3, #(1 * 8)]
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ldr x5, [x3, #(0 * 8)]
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adr x26, 1f
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add x26, x26, x25, lsl #2
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br x26
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1:
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msr dbgwcr15_el1, x20
|
||||
msr dbgwcr14_el1, x19
|
||||
msr dbgwcr13_el1, x18
|
||||
msr dbgwcr12_el1, x17
|
||||
msr dbgwcr11_el1, x16
|
||||
msr dbgwcr10_el1, x15
|
||||
msr dbgwcr9_el1, x14
|
||||
msr dbgwcr8_el1, x13
|
||||
msr dbgwcr7_el1, x12
|
||||
msr dbgwcr6_el1, x11
|
||||
msr dbgwcr5_el1, x10
|
||||
msr dbgwcr4_el1, x9
|
||||
msr dbgwcr3_el1, x8
|
||||
msr dbgwcr2_el1, x7
|
||||
msr dbgwcr1_el1, x6
|
||||
msr dbgwcr0_el1, x5
|
||||
|
||||
add x3, x2, #CPU_SYSREG_OFFSET(DBGWVR0_EL1)
|
||||
|
||||
adr x26, 1f
|
||||
add x26, x26, x25, lsl #2
|
||||
br x26
|
||||
1:
|
||||
ldr x20, [x3, #(15 * 8)]
|
||||
ldr x19, [x3, #(14 * 8)]
|
||||
ldr x18, [x3, #(13 * 8)]
|
||||
ldr x17, [x3, #(12 * 8)]
|
||||
ldr x16, [x3, #(11 * 8)]
|
||||
ldr x15, [x3, #(10 * 8)]
|
||||
ldr x14, [x3, #(9 * 8)]
|
||||
ldr x13, [x3, #(8 * 8)]
|
||||
ldr x12, [x3, #(7 * 8)]
|
||||
ldr x11, [x3, #(6 * 8)]
|
||||
ldr x10, [x3, #(5 * 8)]
|
||||
ldr x9, [x3, #(4 * 8)]
|
||||
ldr x8, [x3, #(3 * 8)]
|
||||
ldr x7, [x3, #(2 * 8)]
|
||||
ldr x6, [x3, #(1 * 8)]
|
||||
ldr x5, [x3, #(0 * 8)]
|
||||
|
||||
adr x26, 1f
|
||||
add x26, x26, x25, lsl #2
|
||||
br x26
|
||||
1:
|
||||
msr dbgwvr15_el1, x20
|
||||
msr dbgwvr14_el1, x19
|
||||
msr dbgwvr13_el1, x18
|
||||
msr dbgwvr12_el1, x17
|
||||
msr dbgwvr11_el1, x16
|
||||
msr dbgwvr10_el1, x15
|
||||
msr dbgwvr9_el1, x14
|
||||
msr dbgwvr8_el1, x13
|
||||
msr dbgwvr7_el1, x12
|
||||
msr dbgwvr6_el1, x11
|
||||
msr dbgwvr5_el1, x10
|
||||
msr dbgwvr4_el1, x9
|
||||
msr dbgwvr3_el1, x8
|
||||
msr dbgwvr2_el1, x7
|
||||
msr dbgwvr1_el1, x6
|
||||
msr dbgwvr0_el1, x5
|
||||
|
||||
ldr x21, [x2, #CPU_SYSREG_OFFSET(MDCCINT_EL1)]
|
||||
msr mdccint_el1, x21
|
||||
msr \type\()15_el1, x21
|
||||
msr \type\()14_el1, x20
|
||||
msr \type\()13_el1, x19
|
||||
msr \type\()12_el1, x18
|
||||
msr \type\()11_el1, x17
|
||||
msr \type\()10_el1, x16
|
||||
msr \type\()9_el1, x15
|
||||
msr \type\()8_el1, x14
|
||||
msr \type\()7_el1, x13
|
||||
msr \type\()6_el1, x12
|
||||
msr \type\()5_el1, x11
|
||||
msr \type\()4_el1, x10
|
||||
msr \type\()3_el1, x9
|
||||
msr \type\()2_el1, x8
|
||||
msr \type\()1_el1, x7
|
||||
msr \type\()0_el1, x6
|
||||
.endm
|
||||
|
||||
.macro skip_32bit_state tmp, target
|
||||
|
|
@ -883,12 +593,61 @@ __restore_sysregs:
|
|||
restore_sysregs
|
||||
ret
|
||||
|
||||
/* Save debug state */
|
||||
__save_debug:
|
||||
save_debug
|
||||
// x2: ptr to CPU context
|
||||
// x4/x5/x6-22/x24-26: trashed
|
||||
|
||||
mrs x26, id_aa64dfr0_el1
|
||||
ubfx x24, x26, #12, #4 // Extract BRPs
|
||||
ubfx x25, x26, #20, #4 // Extract WRPs
|
||||
mov w26, #15
|
||||
sub w24, w26, w24 // How many BPs to skip
|
||||
sub w25, w26, w25 // How many WPs to skip
|
||||
|
||||
mov x5, x24
|
||||
add x4, x2, #CPU_SYSREG_OFFSET(DBGBCR0_EL1)
|
||||
save_debug dbgbcr
|
||||
add x4, x2, #CPU_SYSREG_OFFSET(DBGBVR0_EL1)
|
||||
save_debug dbgbvr
|
||||
|
||||
mov x5, x25
|
||||
add x4, x2, #CPU_SYSREG_OFFSET(DBGWCR0_EL1)
|
||||
save_debug dbgwcr
|
||||
add x4, x2, #CPU_SYSREG_OFFSET(DBGWVR0_EL1)
|
||||
save_debug dbgwvr
|
||||
|
||||
mrs x21, mdccint_el1
|
||||
str x21, [x2, #CPU_SYSREG_OFFSET(MDCCINT_EL1)]
|
||||
ret
|
||||
|
||||
/* Restore debug state */
|
||||
__restore_debug:
|
||||
restore_debug
|
||||
// x2: ptr to CPU context
|
||||
// x4/x5/x6-22/x24-26: trashed
|
||||
|
||||
mrs x26, id_aa64dfr0_el1
|
||||
ubfx x24, x26, #12, #4 // Extract BRPs
|
||||
ubfx x25, x26, #20, #4 // Extract WRPs
|
||||
mov w26, #15
|
||||
sub w24, w26, w24 // How many BPs to skip
|
||||
sub w25, w26, w25 // How many WPs to skip
|
||||
|
||||
mov x5, x24
|
||||
add x4, x2, #CPU_SYSREG_OFFSET(DBGBCR0_EL1)
|
||||
restore_debug dbgbcr
|
||||
add x4, x2, #CPU_SYSREG_OFFSET(DBGBVR0_EL1)
|
||||
restore_debug dbgbvr
|
||||
|
||||
mov x5, x25
|
||||
add x4, x2, #CPU_SYSREG_OFFSET(DBGWCR0_EL1)
|
||||
restore_debug dbgwcr
|
||||
add x4, x2, #CPU_SYSREG_OFFSET(DBGWVR0_EL1)
|
||||
restore_debug dbgwvr
|
||||
|
||||
ldr x21, [x2, #CPU_SYSREG_OFFSET(MDCCINT_EL1)]
|
||||
msr mdccint_el1, x21
|
||||
|
||||
ret
|
||||
|
||||
__save_fpsimd:
|
||||
|
|
|
|||
Loading…
Reference in New Issue