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arm64: Document the requirement for SCR_EL3.HCE 

It is amazing that we never documented this absolutely basic
requirement: if you boot the kernel at EL2, you'd better
enable the HVC instruction from EL3.

Really, just do it.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20210812190213.2601506-6-maz@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Marc Zyngier 2021-08-12 20:02:13 +01:00 committed by Catalin Marinas
parent 90268574a3
commit e384976503
1 changed files with 11 additions and 4 deletions
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Documentation/arm64/booting.rst
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@ -207,10 +207,17 @@ Before jumping into the kernel, the following conditions must be met:
software at a higher exception level to prevent execution in an UNKNOWN software at a higher exception level to prevent execution in an UNKNOWN
state. state.
- SCR_EL3.FIQ must have the same value across all CPUs the kernel is For all systems:
executing on. - If EL3 is present:
- The value of SCR_EL3.FIQ must be the same as the one present at boot
time whenever the kernel is executing. - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
executing on.
- The value of SCR_EL3.FIQ must be the same as the one present at boot
time whenever the kernel is executing.
- If EL3 is present and the kernel is entered at EL2:
- SCR_EL3.HCE (bit 8) must be initialised to 0b1.
For systems with a GICv3 interrupt controller to be used in v3 mode: For systems with a GICv3 interrupt controller to be used in v3 mode:
- If EL3 is present: - If EL3 is present: