drm/msm/mdp5: Remove mixer/intf pointers from mdp5_ctl
These are a part of CRTC state, it doesn't feel nice to leave them hanging in mdp5_ctl struct. Pass mdp5_pipeline pointer instead wherever it is needed. We still have some params in mdp5_ctl like start_mask etc which are derivative of atomic state, and should be rolled back if a commit fails, but it doesn't seem to cause much trouble. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Archit Taneja
Rob Clark
parent
0ddc3a6307
commit
f316b25a23
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@ -132,8 +132,6 @@ void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct mdp5_encoder *mdp5_cmd_enc = to_mdp5_encoder(encoder);
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mode = adjusted_mode;
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DBG("set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
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@ -145,8 +143,7 @@ void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,
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mode->vsync_end, mode->vtotal,
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mode->type, mode->flags);
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pingpong_tearcheck_setup(encoder, mode);
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mdp5_crtc_set_pipeline(encoder->crtc, mdp5_cmd_enc->intf,
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mdp5_cmd_enc->ctl);
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mdp5_crtc_set_pipeline(encoder->crtc);
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}
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void mdp5_cmd_encoder_disable(struct drm_encoder *encoder)
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@ -154,14 +151,15 @@ void mdp5_cmd_encoder_disable(struct drm_encoder *encoder)
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struct mdp5_encoder *mdp5_cmd_enc = to_mdp5_encoder(encoder);
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struct mdp5_ctl *ctl = mdp5_cmd_enc->ctl;
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struct mdp5_interface *intf = mdp5_cmd_enc->intf;
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struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);
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if (WARN_ON(!mdp5_cmd_enc->enabled))
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return;
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pingpong_tearcheck_disable(encoder);
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mdp5_ctl_set_encoder_state(ctl, false);
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mdp5_ctl_commit(ctl, mdp_ctl_flush_mask_encoder(intf));
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mdp5_ctl_set_encoder_state(ctl, pipeline, false);
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mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf));
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bs_set(mdp5_cmd_enc, 0);
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@ -173,6 +171,7 @@ void mdp5_cmd_encoder_enable(struct drm_encoder *encoder)
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struct mdp5_encoder *mdp5_cmd_enc = to_mdp5_encoder(encoder);
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struct mdp5_ctl *ctl = mdp5_cmd_enc->ctl;
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struct mdp5_interface *intf = mdp5_cmd_enc->intf;
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struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);
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if (WARN_ON(mdp5_cmd_enc->enabled))
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return;
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@ -181,9 +180,9 @@ void mdp5_cmd_encoder_enable(struct drm_encoder *encoder)
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if (pingpong_tearcheck_enable(encoder))
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return;
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mdp5_ctl_commit(ctl, mdp_ctl_flush_mask_encoder(intf));
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mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf));
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mdp5_ctl_set_encoder_state(ctl, true);
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mdp5_ctl_set_encoder_state(ctl, pipeline, true);
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mdp5_cmd_enc->enabled = true;
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}
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@ -91,9 +91,10 @@ static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
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{
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struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
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struct mdp5_ctl *ctl = mdp5_cstate->ctl;
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struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
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DBG("%s: flush=%08x", crtc->name, flush_mask);
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return mdp5_ctl_commit(ctl, flush_mask);
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return mdp5_ctl_commit(ctl, pipeline, flush_mask);
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}
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/*
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@ -126,6 +127,7 @@ static u32 crtc_flush_all(struct drm_crtc *crtc)
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static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
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{
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struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
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struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
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struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
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struct mdp5_ctl *ctl = mdp5_cstate->ctl;
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struct drm_device *dev = crtc->dev;
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@ -143,7 +145,7 @@ static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
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if (ctl && !crtc->state->enable) {
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/* set STAGE_UNUSED for all layers */
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mdp5_ctl_blend(ctl, NULL, 0, 0);
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mdp5_ctl_blend(ctl, pipeline, NULL, 0, 0);
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/* XXX: What to do here? */
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/* mdp5_crtc->ctl = NULL; */
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}
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@ -195,12 +197,13 @@ static void blend_setup(struct drm_crtc *crtc)
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{
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struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
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struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
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struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
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struct mdp5_kms *mdp5_kms = get_kms(crtc);
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struct drm_plane *plane;
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const struct mdp5_cfg_hw *hw_cfg;
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struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
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const struct mdp_format *format;
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struct mdp5_hw_mixer *mixer = mdp5_cstate->pipeline.mixer;
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struct mdp5_hw_mixer *mixer = pipeline->mixer;
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uint32_t lm = mixer->lm;
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struct mdp5_ctl *ctl = mdp5_cstate->ctl;
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uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0;
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@ -294,7 +297,7 @@ static void blend_setup(struct drm_crtc *crtc)
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mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), mixer_op_mode);
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mdp5_ctl_blend(ctl, stage, plane_cnt, ctl_blend_flags);
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mdp5_ctl_blend(ctl, pipeline, stage, plane_cnt, ctl_blend_flags);
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out:
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spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
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@ -586,6 +589,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
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{
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struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
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struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
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struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
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struct drm_device *dev = crtc->dev;
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struct mdp5_kms *mdp5_kms = get_kms(crtc);
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struct drm_gem_object *cursor_bo, *old_bo = NULL;
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@ -652,7 +656,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
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spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
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set_cursor:
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ret = mdp5_ctl_set_cursor(ctl, 0, cursor_enable);
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ret = mdp5_ctl_set_cursor(ctl, pipeline, 0, cursor_enable);
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if (ret) {
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dev_err(dev->dev, "failed to %sable cursor: %d\n",
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cursor_enable ? "en" : "dis", ret);
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@ -877,17 +881,15 @@ uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc)
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return mdp5_crtc->vblank.irqmask;
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}
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void mdp5_crtc_set_pipeline(struct drm_crtc *crtc,
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struct mdp5_interface *intf, struct mdp5_ctl *ctl)
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void mdp5_crtc_set_pipeline(struct drm_crtc *crtc)
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{
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struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
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struct mdp5_hw_mixer *mixer = mdp5_cstate->pipeline.mixer;
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struct mdp5_kms *mdp5_kms = get_kms(crtc);
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/* should this be done elsewhere ? */
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mdp_irq_update(&mdp5_kms->base);
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mdp5_ctl_set_pipeline(ctl, intf, mixer);
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mdp5_ctl_set_pipeline(mdp5_cstate->ctl, &mdp5_cstate->pipeline);
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}
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struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc)
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@ -910,6 +912,18 @@ struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc)
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ERR_PTR(-EINVAL) : mdp5_cstate->pipeline.mixer;
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}
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struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc)
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{
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struct mdp5_crtc_state *mdp5_cstate;
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if (WARN_ON(!crtc))
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return ERR_PTR(-EINVAL);
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mdp5_cstate = to_mdp5_crtc_state(crtc->state);
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return &mdp5_cstate->pipeline;
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}
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void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc)
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{
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struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
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@ -36,14 +36,10 @@ struct mdp5_ctl {
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struct mdp5_ctl_manager *ctlm;
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u32 id;
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struct mdp5_hw_mixer *mixer;
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/* CTL status bitmask */
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u32 status;
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/* Operation Mode Configuration for the Pipeline */
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struct mdp5_interface *intf;
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bool encoder_enabled;
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uint32_t start_mask;
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@ -170,14 +166,12 @@ static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_interface *intf)
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spin_unlock_irqrestore(&ctl->hw_lock, flags);
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}
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int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_interface *intf,
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struct mdp5_hw_mixer *mixer)
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int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline)
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{
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struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm;
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struct mdp5_kms *mdp5_kms = get_kms(ctl_mgr);
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ctl->mixer = mixer;
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ctl->intf = intf;
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struct mdp5_interface *intf = pipeline->intf;
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struct mdp5_hw_mixer *mixer = pipeline->mixer;
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ctl->start_mask = mdp_ctl_flush_mask_lm(mixer->lm) |
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mdp_ctl_flush_mask_encoder(intf);
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@ -191,16 +185,19 @@ int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_interface *intf,
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return 0;
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}
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static bool start_signal_needed(struct mdp5_ctl *ctl)
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static bool start_signal_needed(struct mdp5_ctl *ctl,
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struct mdp5_pipeline *pipeline)
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{
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struct mdp5_interface *intf = pipeline->intf;
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if (!ctl->encoder_enabled || ctl->start_mask != 0)
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return false;
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switch (ctl->intf->type) {
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switch (intf->type) {
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case INTF_WB:
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return true;
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case INTF_DSI:
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return ctl->intf->mode == MDP5_INTF_DSI_MODE_COMMAND;
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return intf->mode == MDP5_INTF_DSI_MODE_COMMAND;
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default:
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return false;
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}
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@ -222,11 +219,13 @@ static void send_start_signal(struct mdp5_ctl *ctl)
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spin_unlock_irqrestore(&ctl->hw_lock, flags);
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}
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static void refill_start_mask(struct mdp5_ctl *ctl)
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static void refill_start_mask(struct mdp5_ctl *ctl,
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struct mdp5_pipeline *pipeline)
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{
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struct mdp5_interface *intf = ctl->intf;
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struct mdp5_interface *intf = pipeline->intf;
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struct mdp5_hw_mixer *mixer = pipeline->mixer;
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ctl->start_mask = mdp_ctl_flush_mask_lm(ctl->mixer->lm);
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ctl->start_mask = mdp_ctl_flush_mask_lm(mixer->lm);
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/*
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* Writeback encoder needs to program & flush
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@ -244,17 +243,21 @@ static void refill_start_mask(struct mdp5_ctl *ctl)
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* Note:
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* This encoder state is needed to trigger START signal (data path kickoff).
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*/
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int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, bool enabled)
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int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl,
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struct mdp5_pipeline *pipeline,
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bool enabled)
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{
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struct mdp5_interface *intf = pipeline->intf;
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if (WARN_ON(!ctl))
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return -EINVAL;
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ctl->encoder_enabled = enabled;
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DBG("intf_%d: %s", ctl->intf->num, enabled ? "on" : "off");
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DBG("intf_%d: %s", intf->num, enabled ? "on" : "off");
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if (start_signal_needed(ctl)) {
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if (start_signal_needed(ctl, pipeline)) {
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send_start_signal(ctl);
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refill_start_mask(ctl);
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refill_start_mask(ctl, pipeline);
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}
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return 0;
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@ -265,12 +268,13 @@ int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, bool enabled)
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* CTL registers need to be flushed after calling this function
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* (call mdp5_ctl_commit() with mdp_ctl_flush_mask_ctl() mask)
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*/
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int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, int cursor_id, bool enable)
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int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
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int cursor_id, bool enable)
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{
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struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm;
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unsigned long flags;
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u32 blend_cfg;
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struct mdp5_hw_mixer *mixer = ctl->mixer;
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struct mdp5_hw_mixer *mixer = pipeline->mixer;
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if (unlikely(WARN_ON(!mixer))) {
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dev_err(ctl_mgr->dev->dev, "CTL %d cannot find LM",
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@ -340,10 +344,10 @@ static u32 mdp_ctl_blend_ext_mask(enum mdp5_pipe pipe,
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}
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}
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int mdp5_ctl_blend(struct mdp5_ctl *ctl, enum mdp5_pipe *stage, u32 stage_cnt,
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u32 ctl_blend_op_flags)
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int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
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enum mdp5_pipe *stage, u32 stage_cnt, u32 ctl_blend_op_flags)
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{
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struct mdp5_hw_mixer *mixer = ctl->mixer;
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struct mdp5_hw_mixer *mixer = pipeline->mixer;
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unsigned long flags;
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u32 blend_cfg = 0, blend_ext_cfg = 0;
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int i, start_stage;
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@ -430,7 +434,8 @@ u32 mdp_ctl_flush_mask_lm(int lm)
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}
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}
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static u32 fix_sw_flush(struct mdp5_ctl *ctl, u32 flush_mask)
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static u32 fix_sw_flush(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
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u32 flush_mask)
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{
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struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm;
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u32 sw_mask = 0;
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@ -439,7 +444,7 @@ static u32 fix_sw_flush(struct mdp5_ctl *ctl, u32 flush_mask)
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/* for some targets, cursor bit is the same as LM bit */
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if (BIT_NEEDS_SW_FIX(MDP5_CTL_FLUSH_CURSOR_0))
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sw_mask |= mdp_ctl_flush_mask_lm(ctl->mixer->lm);
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sw_mask |= mdp_ctl_flush_mask_lm(pipeline->mixer->lm);
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return sw_mask;
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}
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@ -485,7 +490,9 @@ static void fix_for_single_flush(struct mdp5_ctl *ctl, u32 *flush_mask,
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*
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* Return H/W flushed bit mask.
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*/
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u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask)
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u32 mdp5_ctl_commit(struct mdp5_ctl *ctl,
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struct mdp5_pipeline *pipeline,
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u32 flush_mask)
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{
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struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm;
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unsigned long flags;
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@ -502,7 +509,7 @@ u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask)
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ctl->pending_ctl_trigger = 0;
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}
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flush_mask |= fix_sw_flush(ctl, flush_mask);
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flush_mask |= fix_sw_flush(ctl, pipeline, flush_mask);
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flush_mask &= ctl_mgr->flush_hw_mask;
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@ -516,9 +523,9 @@ u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask)
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spin_unlock_irqrestore(&ctl->hw_lock, flags);
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}
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if (start_signal_needed(ctl)) {
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if (start_signal_needed(ctl, pipeline)) {
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send_start_signal(ctl);
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refill_start_mask(ctl);
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refill_start_mask(ctl, pipeline);
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}
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return curr_ctl_flush_mask;
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@ -605,7 +612,6 @@ struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctl_mgr,
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found:
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ctl = &ctl_mgr->ctls[c];
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ctl->mixer = NULL;
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ctl->status |= CTL_STAT_BUSY;
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ctl->pending_ctl_trigger = 0;
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DBG("CTL %d allocated", ctl->id);
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@ -37,11 +37,13 @@ struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctlm, int intf_num);
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int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl);
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struct mdp5_interface;
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int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_interface *intf,
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struct mdp5_hw_mixer *lm);
|
||||
int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, bool enabled);
|
||||
struct mdp5_pipeline;
|
||||
int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *p);
|
||||
int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, struct mdp5_pipeline *p,
|
||||
bool enabled);
|
||||
|
||||
int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, int cursor_id, bool enable);
|
||||
int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
|
||||
int cursor_id, bool enable);
|
||||
int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable);
|
||||
|
||||
/*
|
||||
|
|
@ -56,7 +58,8 @@ int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable);
|
|||
* (call mdp5_ctl_commit() with mdp_ctl_flush_mask_ctl() mask)
|
||||
*/
|
||||
#define MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT BIT(0)
|
||||
int mdp5_ctl_blend(struct mdp5_ctl *ctl, enum mdp5_pipe *stage, u32 stage_cnt,
|
||||
int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
|
||||
enum mdp5_pipe *stage, u32 stage_cnt,
|
||||
u32 ctl_blend_op_flags);
|
||||
|
||||
/**
|
||||
|
|
@ -71,7 +74,8 @@ u32 mdp_ctl_flush_mask_cursor(int cursor_id);
|
|||
u32 mdp_ctl_flush_mask_encoder(struct mdp5_interface *intf);
|
||||
|
||||
/* @flush_mask: see CTL flush masks definitions below */
|
||||
u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask);
|
||||
u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
|
||||
u32 flush_mask);
|
||||
u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl);
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -206,8 +206,7 @@ static void mdp5_vid_encoder_mode_set(struct drm_encoder *encoder,
|
|||
|
||||
spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
|
||||
|
||||
mdp5_crtc_set_pipeline(encoder->crtc, mdp5_encoder->intf,
|
||||
mdp5_encoder->ctl);
|
||||
mdp5_crtc_set_pipeline(encoder->crtc);
|
||||
}
|
||||
|
||||
static void mdp5_vid_encoder_disable(struct drm_encoder *encoder)
|
||||
|
|
@ -215,6 +214,7 @@ static void mdp5_vid_encoder_disable(struct drm_encoder *encoder)
|
|||
struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
|
||||
struct mdp5_kms *mdp5_kms = get_kms(encoder);
|
||||
struct mdp5_ctl *ctl = mdp5_encoder->ctl;
|
||||
struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);
|
||||
struct mdp5_hw_mixer *mixer = mdp5_crtc_get_mixer(encoder->crtc);
|
||||
struct mdp5_interface *intf = mdp5_encoder->intf;
|
||||
int intfn = mdp5_encoder->intf->num;
|
||||
|
|
@ -223,12 +223,12 @@ static void mdp5_vid_encoder_disable(struct drm_encoder *encoder)
|
|||
if (WARN_ON(!mdp5_encoder->enabled))
|
||||
return;
|
||||
|
||||
mdp5_ctl_set_encoder_state(ctl, false);
|
||||
mdp5_ctl_set_encoder_state(ctl, pipeline, false);
|
||||
|
||||
spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
|
||||
mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 0);
|
||||
spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
|
||||
mdp5_ctl_commit(ctl, mdp_ctl_flush_mask_encoder(intf));
|
||||
mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf));
|
||||
|
||||
/*
|
||||
* Wait for a vsync so we know the ENABLE=0 latched before
|
||||
|
|
@ -251,6 +251,7 @@ static void mdp5_vid_encoder_enable(struct drm_encoder *encoder)
|
|||
struct mdp5_kms *mdp5_kms = get_kms(encoder);
|
||||
struct mdp5_ctl *ctl = mdp5_encoder->ctl;
|
||||
struct mdp5_interface *intf = mdp5_encoder->intf;
|
||||
struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);
|
||||
int intfn = intf->num;
|
||||
unsigned long flags;
|
||||
|
||||
|
|
@ -261,9 +262,9 @@ static void mdp5_vid_encoder_enable(struct drm_encoder *encoder)
|
|||
spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
|
||||
mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 1);
|
||||
spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
|
||||
mdp5_ctl_commit(ctl, mdp_ctl_flush_mask_encoder(intf));
|
||||
mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf));
|
||||
|
||||
mdp5_ctl_set_encoder_state(ctl, true);
|
||||
mdp5_ctl_set_encoder_state(ctl, pipeline, true);
|
||||
|
||||
mdp5_encoder->enabled = true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -280,8 +280,8 @@ struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc);
|
|||
uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc);
|
||||
|
||||
struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc);
|
||||
void mdp5_crtc_set_pipeline(struct drm_crtc *crtc,
|
||||
struct mdp5_interface *intf, struct mdp5_ctl *ctl);
|
||||
struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc);
|
||||
void mdp5_crtc_set_pipeline(struct drm_crtc *crtc);
|
||||
void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc);
|
||||
struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
|
||||
struct drm_plane *plane,
|
||||
|
|
|
|||
|
|
@ -937,6 +937,7 @@ static int mdp5_update_cursor_plane_legacy(struct drm_plane *plane,
|
|||
|
||||
if (new_plane_state->visible) {
|
||||
struct mdp5_ctl *ctl;
|
||||
struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(crtc);
|
||||
|
||||
ret = mdp5_plane_mode_set(plane, crtc, fb,
|
||||
&new_plane_state->src,
|
||||
|
|
@ -945,7 +946,7 @@ static int mdp5_update_cursor_plane_legacy(struct drm_plane *plane,
|
|||
|
||||
ctl = mdp5_crtc_get_ctl(crtc);
|
||||
|
||||
mdp5_ctl_commit(ctl, mdp5_plane_get_flush(plane));
|
||||
mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane));
|
||||
}
|
||||
|
||||
*to_mdp5_plane_state(plane_state) =
|
||||
|
|
|
|||
Loading…
Reference in New Issue