clk: renesas: Updates for v5.11 (take three)
- Update git repo branch for Renesas clock drivers, - Add camera (CSI) and video-in (VIN) clocks on R-Car V3U, - Add RPC (QSPI/HyperFLASH) clocks on RZ/G2M, RZ/G2N, and RZ/G2E, - Stop using __raw_*() I/O accessors, - One more conversion of DT bindings to json-schema, - Minor fixes and improvements. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCX9HQTAAKCRCKwlD9ZEnx cHWJAP0fr6F+nXrpv065rE5G+BXXDdX/Jfrma+g9xgsIQMOCsAEAgScD3VsLGwcj k1BP4ZmXaNg0UkRWHsk67dYhC5EgcAg= =vjjb -----END PGP SIGNATURE----- Merge tag 'renesas-clk-for-v5.11-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Update git repo branch for Renesas clock drivers - Add camera (CSI) and video-in (VIN) clocks on R-Car V3U - Add RPC (QSPI/HyperFLASH) clocks on RZ/G2M, RZ/G2N, and RZ/G2E - Stop using __raw_*() I/O accessors - One more conversion of DT bindings to json-schema - Minor fixes and improvements * tag 'renesas-clk-for-v5.11-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: dt-bindings: clock: renesas: rcar-usb2-clock-sel: Convert bindings to json-schema clk: renesas: sh73a0: Stop using __raw_*() I/O accessors clk: renesas: r8a774c0: Add RPC clocks clk: renesas: r8a779a0: Fix R and OSC clocks clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_priv clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get() clk: renesas: r8a774b1: Add RPC clocks clk: renesas: r8a774a1: Add RPC clocks clk: renesas: r8a779a0: Add VIN clocks clk: renesas: r8a779a0: Add CSI4[0-3] clocks MAINTAINERS: Update git repo for Renesas clock drivers clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() static clk: renesas: rcar-gen3: Remove stp_ck handling for SDHI
This commit is contained in:
Stephen Boyd
commit
fdc9b01911
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@ -1,68 +0,0 @@
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* Renesas R-Car USB 2.0 clock selector
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This file provides information on what the device node for the R-Car USB 2.0
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clock selector.
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If you connect an external clock to the USB_EXTAL pin only, you should set
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the clock rate to "usb_extal" node only.
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If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module
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is not needed because this is default setting. (Of course, you can set the
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clock rates to both "usb_extal" and "usb_xtal" nodes.
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Case 1: An external clock connects to R-Car SoC
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+----------+ +--- R-Car ---------------------+
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|External |---|USB_EXTAL ---> all usb channels|
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|clock | |USB_XTAL |
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+----------+ +-------------------------------+
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In this case, we need this driver with "usb_extal" clock.
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Case 2: An oscillator connects to R-Car SoC
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+----------+ +--- R-Car ---------------------+
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|Oscillator|---|USB_EXTAL -+-> all usb channels|
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| |---|USB_XTAL --+ |
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+----------+ +-------------------------------+
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In this case, we don't need this selector.
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Required properties:
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- compatible: "renesas,r8a7795-rcar-usb2-clock-sel" if the device is a part of
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an R8A7795 SoC.
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"renesas,r8a7796-rcar-usb2-clock-sel" if the device if a part of
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an R8A77960 SoC.
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"renesas,r8a77961-rcar-usb2-clock-sel" if the device if a part of
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an R8A77961 SoC.
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"renesas,rcar-gen3-usb2-clock-sel" for a generic R-Car Gen3
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compatible device.
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When compatible with the generic version, nodes must list the
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SoC-specific version corresponding to the platform first
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followed by the generic version.
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- reg: offset and length of the USB 2.0 clock selector register block.
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- clocks: A list of phandles and specifier pairs.
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- clock-names: Name of the clocks.
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- The functional clock of USB 2.0 host side must be "ehci_ohci"
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- The functional clock of HS-USB side must be "hs-usb-if"
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- The USB_EXTAL clock pin must be "usb_extal"
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- The USB_XTAL clock pin must be "usb_xtal"
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- #clock-cells: Must be 0
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- power-domains: A phandle and symbolic PM domain specifier.
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See power/renesas,rcar-sysc.yaml.
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- resets: A list of phandles and specifier pairs.
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- reset-names: Name of the resets.
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- The reset of USB 2.0 host side must be "ehci_ohci"
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- The reset of HS-USB side must be "hs-usb-if"
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Example (R-Car H3):
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usb2_clksel: clock-controller@e6590630 {
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compatible = "renesas,r8a7795-rcar-usb2-clock-sel",
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"renesas,rcar-gen3-usb2-clock-sel";
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reg = <0 0xe6590630 0 0x02>;
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clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
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<&usb_extal>, <&usb_xtal>;
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clock-names = "ehci_ohci", "hs-usb-if", "usb_extal", "usb_xtal";
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#clock-cells = <0>;
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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resets = <&cpg 703>, <&cpg 704>;
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reset-names = "ehci_ohci", "hs-usb-if";
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};
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@ -0,0 +1,100 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Renesas R-Car USB 2.0 clock selector
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maintainers:
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- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
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description: |
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If you connect an external clock to the USB_EXTAL pin only, you should set
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the clock rate to "usb_extal" node only.
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If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module
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is not needed because this is default setting. (Of course, you can set the
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clock rates to both "usb_extal" and "usb_xtal" nodes.
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Case 1: An external clock connects to R-Car SoC
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+----------+ +--- R-Car ---------------------+
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|External |---|USB_EXTAL ---> all usb channels|
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|clock | |USB_XTAL |
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+----------+ +-------------------------------+
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In this case, we need this driver with "usb_extal" clock.
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Case 2: An oscillator connects to R-Car SoC
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+----------+ +--- R-Car ---------------------+
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|Oscillator|---|USB_EXTAL -+-> all usb channels|
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| |---|USB_XTAL --+ |
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+----------+ +-------------------------------+
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In this case, we don't need this selector.
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properties:
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compatible:
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items:
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- enum:
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- renesas,r8a7795-rcar-usb2-clock-sel # R-Car H3
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- renesas,r8a7796-rcar-usb2-clock-sel # R-Car M3-W
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- renesas,r8a77961-rcar-usb2-clock-sel # R-Car M3-W+
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- const: renesas,rcar-gen3-usb2-clock-sel
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reg:
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maxItems: 1
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clocks:
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minItems: 4
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maxItems: 4
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clock-names:
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items:
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- const: ehci_ohci
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- const: hs-usb-if
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- const: usb_extal
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- const: usb_xtal
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'#clock-cells':
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const: 0
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power-domains:
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maxItems: 1
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resets:
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minItems: 2
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maxItems: 2
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reset-names:
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items:
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- const: ehci_ohci
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- const: hs-usb-if
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- power-domains
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- resets
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- reset-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
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#include <dt-bindings/power/r8a7795-sysc.h>
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usb2_clksel: clock-controller@e6590630 {
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compatible = "renesas,r8a7795-rcar-usb2-clock-sel",
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"renesas,rcar-gen3-usb2-clock-sel";
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reg = <0xe6590630 0x02>;
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clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
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<&usb_extal>, <&usb_xtal>;
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clock-names = "ehci_ohci", "hs-usb-if", "usb_extal", "usb_xtal";
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#clock-cells = <0>;
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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resets = <&cpg 703>, <&cpg 704>;
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reset-names = "ehci_ohci", "hs-usb-if";
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};
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@ -14888,7 +14888,7 @@ RENESAS CLOCK DRIVERS
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M: Geert Uytterhoeven <geert+renesas@glider.be>
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L: linux-renesas-soc@vger.kernel.org
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S: Supported
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git clk-renesas
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-clk
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F: Documentation/devicetree/bindings/clock/renesas,*
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F: drivers/clk/renesas/
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@ -121,7 +121,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
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(phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR);
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parent_name = phy_no ? "dsi1pck" : "dsi0pck";
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mult = __raw_readl(dsi_reg);
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mult = readl(dsi_reg);
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if (!(mult & 0x8000))
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mult = 1;
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else
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@ -41,6 +41,7 @@ enum clk_ids {
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CLK_S2,
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CLK_S3,
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CLK_SDSRC,
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CLK_RPCSRC,
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CLK_RINT,
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/* Module Clocks */
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@ -67,6 +68,12 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC,
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CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
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R8A774A1_CLK_RPC),
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DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
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@ -200,6 +207,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
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DEF_MOD("can-fd", 914, R8A774A1_CLK_S3D2),
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DEF_MOD("can-if1", 915, R8A774A1_CLK_S3D4),
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DEF_MOD("can-if0", 916, R8A774A1_CLK_S3D4),
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DEF_MOD("rpc-if", 917, R8A774A1_CLK_RPCD2),
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DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6),
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DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6),
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DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP),
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@ -40,6 +40,7 @@ enum clk_ids {
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CLK_S2,
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CLK_S3,
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CLK_SDSRC,
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CLK_RPCSRC,
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CLK_RINT,
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/* Module Clocks */
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@ -65,6 +66,12 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC,
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CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
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R8A774B1_CLK_RPC),
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DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
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@ -196,6 +203,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
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DEF_MOD("can-fd", 914, R8A774B1_CLK_S3D2),
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DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4),
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DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4),
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DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2),
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DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
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DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
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DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP),
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|
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@ -44,6 +44,7 @@ enum clk_ids {
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CLK_S2,
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CLK_S3,
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CLK_SDSRC,
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CLK_RPCSRC,
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CLK_RINT,
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CLK_OCO,
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@ -74,6 +75,13 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
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DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
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DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
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CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
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R8A774C0_CLK_RPC),
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DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
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DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
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|
@ -199,6 +207,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
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DEF_MOD("can-fd", 914, R8A774C0_CLK_S3D2),
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DEF_MOD("can-if1", 915, R8A774C0_CLK_S3D4),
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DEF_MOD("can-if0", 916, R8A774C0_CLK_S3D4),
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DEF_MOD("rpc-if", 917, R8A774C0_CLK_RPCD2),
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DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2),
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DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2),
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DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP),
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||||
|
|
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|||
|
|
@ -26,7 +26,6 @@
|
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#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
|
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|
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#include "renesas-cpg-mssr.h"
|
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#include "rcar-gen3-cpg.h"
|
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|
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enum rcar_r8a779a0_clk_types {
|
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CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM,
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|
|
@ -84,6 +83,14 @@ enum clk_ids {
|
|||
DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \
|
||||
.offset = _offset)
|
||||
|
||||
#define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
|
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DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \
|
||||
(_parent0) << 16 | (_parent1), \
|
||||
.div = (_div0) << 16 | (_div1), .offset = _md)
|
||||
|
||||
#define DEF_OSC(_name, _id, _parent, _div) \
|
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DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div)
|
||||
|
||||
static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
|
|
@ -136,15 +143,51 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
|
|||
DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
|
||||
DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
|
||||
|
||||
DEF_GEN3_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
|
||||
DEF_GEN3_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
|
||||
DEF_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
|
||||
DEF_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
|
||||
DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0),
|
||||
DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0),
|
||||
DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0),
|
||||
DEF_MOD("csi43", 402, R8A779A0_CLK_CSI0),
|
||||
DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8),
|
||||
DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8),
|
||||
DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8),
|
||||
DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8),
|
||||
DEF_MOD("vin00", 730, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin01", 731, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin02", 800, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin03", 801, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin04", 802, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin05", 803, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin06", 804, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin07", 805, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin10", 806, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin11", 807, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin12", 808, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin13", 809, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin14", 810, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin15", 811, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin16", 812, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin17", 813, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin20", 814, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin21", 815, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin22", 816, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin23", 817, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin24", 818, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin25", 819, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin26", 820, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin27", 821, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin30", 822, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin31", 823, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin32", 824, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin33", 825, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin34", 826, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin35", 827, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin36", 828, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin37", 829, R8A779A0_CLK_S1D1),
|
||||
};
|
||||
|
||||
static spinlock_t cpg_lock;
|
||||
|
|
@ -153,7 +196,7 @@ static const struct rcar_r8a779a0_cpg_pll_config *cpg_pll_config __initdata;
|
|||
static unsigned int cpg_clk_extalr __initdata;
|
||||
static u32 cpg_mode __initdata;
|
||||
|
||||
struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
|
||||
static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
|
||||
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
|
||||
struct clk **clks, void __iomem *base,
|
||||
struct raw_notifier_head *notifiers)
|
||||
|
|
|
|||
|
|
@ -224,10 +224,9 @@ static struct clk * __init cpg_z_clk_register(const char *name,
|
|||
#define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
|
||||
#define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
|
||||
|
||||
#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
|
||||
#define CPG_SD_DIV_TABLE_DATA(stp_hck, sd_srcfc, sd_fc, sd_div) \
|
||||
{ \
|
||||
.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
|
||||
((stp_ck) ? CPG_SD_STP_CK : 0) | \
|
||||
((sd_srcfc) << 2) | \
|
||||
((sd_fc) << 0), \
|
||||
.div = (sd_div), \
|
||||
|
|
@ -247,36 +246,36 @@ struct sd_clock {
|
|||
};
|
||||
|
||||
/* SDn divider
|
||||
* sd_srcfc sd_fc div
|
||||
* stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
|
||||
*-------------------------------------------------------------------
|
||||
* 0 0 0 (1) 1 (4) 4 : SDR104 / HS200 / HS400 (8 TAP)
|
||||
* 0 0 1 (2) 1 (4) 8 : SDR50
|
||||
* 1 0 2 (4) 1 (4) 16 : HS / SDR25
|
||||
* 1 0 3 (8) 1 (4) 32 : NS / SDR12
|
||||
* 1 0 4 (16) 1 (4) 64
|
||||
* 0 0 0 (1) 0 (2) 2
|
||||
* 0 0 1 (2) 0 (2) 4 : SDR104 / HS200 / HS400 (4 TAP)
|
||||
* 1 0 2 (4) 0 (2) 8
|
||||
* 1 0 3 (8) 0 (2) 16
|
||||
* 1 0 4 (16) 0 (2) 32
|
||||
* sd_srcfc sd_fc div
|
||||
* stp_hck (div) (div) = sd_srcfc x sd_fc
|
||||
*---------------------------------------------------------
|
||||
* 0 0 (1) 1 (4) 4 : SDR104 / HS200 / HS400 (8 TAP)
|
||||
* 0 1 (2) 1 (4) 8 : SDR50
|
||||
* 1 2 (4) 1 (4) 16 : HS / SDR25
|
||||
* 1 3 (8) 1 (4) 32 : NS / SDR12
|
||||
* 1 4 (16) 1 (4) 64
|
||||
* 0 0 (1) 0 (2) 2
|
||||
* 0 1 (2) 0 (2) 4 : SDR104 / HS200 / HS400 (4 TAP)
|
||||
* 1 2 (4) 0 (2) 8
|
||||
* 1 3 (8) 0 (2) 16
|
||||
* 1 4 (16) 0 (2) 32
|
||||
*
|
||||
* NOTE: There is a quirk option to ignore the first row of the dividers
|
||||
* table when searching for suitable settings. This is because HS400 on
|
||||
* early ES versions of H3 and M3-W requires a specific setting to work.
|
||||
*/
|
||||
static const struct sd_div_table cpg_sd_div_table[] = {
|
||||
/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
|
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
|
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
|
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
|
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
|
||||
/* CPG_SD_DIV_TABLE_DATA(stp_hck, sd_srcfc, sd_fc, sd_div) */
|
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 1, 4),
|
||||
CPG_SD_DIV_TABLE_DATA(0, 1, 1, 8),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 2, 1, 16),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 3, 1, 32),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 4, 1, 64),
|
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 0, 2),
|
||||
CPG_SD_DIV_TABLE_DATA(0, 1, 0, 4),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 2, 0, 8),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 3, 0, 16),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 4, 0, 32),
|
||||
};
|
||||
|
||||
#define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
|
||||
|
|
@ -696,6 +695,34 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
|
|||
cpg_rpcsrc_div_table,
|
||||
&cpg_lock);
|
||||
|
||||
case CLK_TYPE_GEN3_E3_RPCSRC:
|
||||
/*
|
||||
* Register RPCSRC as fixed factor clock based on the
|
||||
* MD[4:1] pins and CPG_RPCCKCR[4:3] register value for
|
||||
* which has been set prior to booting the kernel.
|
||||
*/
|
||||
value = (readl(base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3;
|
||||
|
||||
switch (value) {
|
||||
case 0:
|
||||
div = 5;
|
||||
break;
|
||||
case 1:
|
||||
div = 3;
|
||||
break;
|
||||
case 2:
|
||||
parent = clks[core->parent >> 16];
|
||||
if (IS_ERR(parent))
|
||||
return ERR_CAST(parent);
|
||||
div = core->div;
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
div = 2;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_RPC:
|
||||
return cpg_rpc_clk_register(core->name, base,
|
||||
__clk_get_name(parent), notifiers);
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@ enum rcar_gen3_clk_types {
|
|||
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
|
||||
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
|
||||
CLK_TYPE_GEN3_RPCSRC,
|
||||
CLK_TYPE_GEN3_E3_RPCSRC,
|
||||
CLK_TYPE_GEN3_RPC,
|
||||
CLK_TYPE_GEN3_RPCD2,
|
||||
|
||||
|
|
@ -54,6 +55,10 @@ enum rcar_gen3_clk_types {
|
|||
#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \
|
||||
DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
|
||||
|
||||
#define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \
|
||||
(_parent0) << 16 | (_parent1), .div = 8)
|
||||
|
||||
struct rcar_gen3_cpg_pll_config {
|
||||
u8 extal_div;
|
||||
u8 pll1_mult;
|
||||
|
|
|
|||
|
|
@ -160,7 +160,7 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
|
|||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
priv->rsts = devm_reset_control_array_get(dev, true, false);
|
||||
priv->rsts = devm_reset_control_array_get_shared(dev);
|
||||
if (IS_ERR(priv->rsts))
|
||||
return PTR_ERR(priv->rsts);
|
||||
|
||||
|
|
|
|||
|
|
@ -119,7 +119,8 @@ static const u16 srstclr_for_v3u[] = {
|
|||
};
|
||||
|
||||
/**
|
||||
* Clock Pulse Generator / Module Standby and Software Reset Private Data
|
||||
* struct cpg_mssr_priv - Clock Pulse Generator / Module Standby
|
||||
* and Software Reset Private Data
|
||||
*
|
||||
* @rcdev: Optional reset controller entity
|
||||
* @dev: CPG/MSSR device
|
||||
|
|
|
|||
Loading…
Reference in New Issue