OMAP2/3/4 clock: omap2_clk_prepare_for_reboot() is OMAP2xxx-only
omap2_clk_prepare_for_reboot() is only applicable to OMAP2xxx chips, so rename it to omap2xxx_clk_prepare_for_reboot() and only call it when running on OMAP2xxx chips. Remove the old stub in the OMAP3 clock code. Signed-off-by: Paul Walmsley <paul@pwsan.com>
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@ -84,7 +84,6 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
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u32 omap2_get_dpll_rate(struct clk *clk);
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u32 omap2_get_dpll_rate(struct clk *clk);
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void omap2_init_dpll_parent(struct clk *clk);
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void omap2_init_dpll_parent(struct clk *clk);
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int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
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int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
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void omap2_clk_prepare_for_reboot(void);
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int omap2_dflt_clk_enable(struct clk *clk);
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int omap2_dflt_clk_enable(struct clk *clk);
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void omap2_dflt_clk_disable(struct clk *clk);
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void omap2_dflt_clk_disable(struct clk *clk);
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void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
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void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
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@ -71,7 +71,7 @@ const struct clkops clkops_omap2430_i2chs_wait = {
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/*
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/*
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* Set clocks for bypass mode for reboot to work.
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* Set clocks for bypass mode for reboot to work.
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*/
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*/
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void omap2_clk_prepare_for_reboot(void)
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void omap2xxx_clk_prepare_for_reboot(void)
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{
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{
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u32 rate;
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u32 rate;
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@ -18,6 +18,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
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unsigned long omap2xxx_clk_get_core_rate(struct clk *clk);
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unsigned long omap2xxx_clk_get_core_rate(struct clk *clk);
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u32 omap2xxx_get_apll_clkin(void);
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u32 omap2xxx_get_apll_clkin(void);
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u32 omap2xxx_get_sysclkdiv(void);
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u32 omap2xxx_get_sysclkdiv(void);
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void omap2xxx_clk_prepare_for_reboot(void);
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/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
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/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
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#ifdef CONFIG_ARCH_OMAP2420
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#ifdef CONFIG_ARCH_OMAP2420
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@ -150,25 +150,6 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
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return omap3_noncore_dpll_set_rate(clk, rate);
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return omap3_noncore_dpll_set_rate(clk, rate);
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}
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}
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/* Common clock code */
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/*
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* Set clocks for bypass mode for reboot to work.
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*/
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void omap2_clk_prepare_for_reboot(void)
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{
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/* REVISIT: Not ready for 343x */
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#if 0
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u32 rate;
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if (vclk == NULL || sclk == NULL)
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return;
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rate = clk_get_rate(sclk);
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clk_set_rate(vclk, rate);
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#endif
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}
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void omap3_clk_lock_dpll5(void)
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void omap3_clk_lock_dpll5(void)
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{
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{
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struct clk *dpll5_clk;
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struct clk *dpll5_clk;
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@ -191,6 +172,8 @@ void omap3_clk_lock_dpll5(void)
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return;
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return;
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}
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}
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/* Common clock code */
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/* REVISIT: Move this init stuff out into clock.c */
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/* REVISIT: Move this init stuff out into clock.c */
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/*
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/*
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@ -17,8 +17,3 @@ const struct clkops clkops_noncore_dpll_ops = {
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.enable = &omap3_noncore_dpll_enable,
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.enable = &omap3_noncore_dpll_enable,
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.disable = &omap3_noncore_dpll_disable,
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.disable = &omap3_noncore_dpll_disable,
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};
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};
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void omap2_clk_prepare_for_reboot(void)
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{
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return;
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}
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@ -29,6 +29,7 @@
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#include <plat/control.h>
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#include <plat/control.h>
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#include "clock.h"
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#include "clock.h"
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#include "clock2xxx.h"
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#include "cm.h"
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#include "cm.h"
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#include "prm.h"
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#include "prm.h"
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#include "prm-regbits-24xx.h"
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#include "prm-regbits-24xx.h"
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@ -133,11 +134,12 @@ EXPORT_SYMBOL(omap_prcm_get_reset_sources);
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void omap_prcm_arch_reset(char mode)
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void omap_prcm_arch_reset(char mode)
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{
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{
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s16 prcm_offs;
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s16 prcm_offs;
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omap2_clk_prepare_for_reboot();
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if (cpu_is_omap24xx())
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if (cpu_is_omap24xx()) {
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omap2xxx_clk_prepare_for_reboot();
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prcm_offs = WKUP_MOD;
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prcm_offs = WKUP_MOD;
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else if (cpu_is_omap34xx()) {
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} else if (cpu_is_omap34xx()) {
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u32 l;
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u32 l;
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prcm_offs = OMAP3430_GR_MOD;
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prcm_offs = OMAP3430_GR_MOD;
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