Some SoC(e.g NXP imx8MQ) may have a wrong default power down scale
setting so need init it to be the correct value, the power down
scale setting description in DWC3 databook:
Power Down Scale (PwrDnScale)
The USB3 suspend_clk input replaces pipe3_rx_pclk as a clock source to
a small part of the USB3 core that operates when the SS PHY is in its
lowest power (P3) state, and therefore does not provide a clock.
The Power Down Scale field specifies how many suspend_clk periods fit
into a 16 kHz clock period. When performing the division, round up the
remainder.
For example, when using an 8-bit/16-bit/32-bit PHY and 25-MHz Suspend
clock,
Power Down Scale = 25000 kHz/16 kHz = 13'd1563 (rounder up)
So use the suspend clock rate to calculate it.
Reviewed-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
Link: https://lore.kernel.org/r/1654568404-3461-1-git-send-email-jun.li@nxp.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Bug: 234219431
(cherry picked from commit 3497b9a5c8c3d4efaa15ab542cc6a774b0e0a7c6
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git usb-testing)
[jindong: rebase to v5.15, get "suspend" clk from of to replace nonexistent dwc->susp_clk]
Change-Id: I0ce2c8041810d4add84b628fc8c3964063aacd5c
Signed-off-by: Jindong Yue <jindong.yue@nxp.com>
2d18a97422