The cache type register found in ARMv5 and later CPUs changes format
and meaning depending on the CPU architecture version. Currently,
this code:
a) doesn't work for everything - Xscale's are identified as
'unknown 5'.
b) is not able to tell whether the caches are VIVT or VIPT from the
cache type.
c) prints rubbish on some ARMv6 and ARMv7+ CPUs.
The two solutions to this are:
1. Add yet more code to decode and print the various different register
formats.
2. Remove the code altogther.
The code only exists to decode and print the cache parameters.
Increasing the complexity of it just for the sake of a few prinks
isn't worth it.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
90f1e08478