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ARM architecture reference manuals for ARMv6 & ARMv7 state that the use of 'swp' instruction is deprecated 

ARMv6 onwards. These architectures provide the load-linked, store-conditional pair of ldrex/strex whose use
is recommended in place of 'swp'. Also, the description of the 'swp' instruction in the ARMv6 reference
manual states that the swap operation does not include any memory barrier guarantees.This fix attempts to
address these issues by providing an atomic swap implementation using ldrex/strex under _ARM_HAVE_LDREX_STREX
macro. _ARM_HAVE_LDREX_STREX macro is defined in  cpu-features.h file and patch is submitted under change ID 11088.
This Fix is verified on ST Ericsson's U8500 platform and Submitted on behalf of a third-party:
Surinder-pal SINGH from STMicroelectronics.
This commit is contained in:
Vinay HARUGOP 2009-09-10 00:31:12 +05:30
parent a145741e1c
commit 02608475ed
1 changed files with 11 additions and 5 deletions
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16
libcutils/atomic-android-arm.S
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@ -17,8 +17,7 @@
#include <machine/cpu-features.h>
/*
* NOTE: these atomic operations are SMP safe on all architectures,
* except swap(), see below.
* NOTE: these atomic operations are SMP safe on all architectures.
*/
.text
@ -228,11 +227,18 @@ android_atomic_or:
* output: r0 = old value
*/
/* FIXME: this is not safe on SMP systems
* a general way to do it is to use kernel_cmpxchg */
/* replaced swp instruction with ldrex/strex for ARMv6 & ARMv7 */
android_atomic_swap:
#if defined (_ARM_HAVE_LDREX_STREX)
1: ldrex r2, [r1]
strex r3, r0, [r1]
teq r3, #0
bne 1b
mov r0, r2
mcr p15, 0, r0, c7, c10, 5 /* or, use dmb */
#else
swp r0, r0, [r1]
#endif
bx lr
/*