Add Silvermont architecture cache sizes
Adds Silvermont specific cache sizes for memset16/32 SSE optimization. Change-Id: Ib5ea086d57544e74ac384ee1ef516b8511392f70 Signed-off-by: Henrik Smiding <henrik.smiding@intel.com>
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@ -17,8 +17,15 @@
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* Contributed by: Intel Corporation
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*/
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#if defined(__slm__)
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/* Values are optimized for Silvermont */
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#define SHARED_CACHE_SIZE (1024*1024) /* Silvermont L2 Cache */
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#define DATA_CACHE_SIZE (24*1024) /* Silvermont L1 Data Cache */
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#else
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/* Values are optimized for Atom */
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#define SHARED_CACHE_SIZE (512*1024) /* Atom L2 Cache */
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#define DATA_CACHE_SIZE (24*1024) /* Atom L1 Data Cache */
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#define SHARED_CACHE_SIZE (512*1024) /* Atom L2 Cache */
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#define DATA_CACHE_SIZE (24*1024) /* Atom L1 Data Cache */
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#endif
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#define SHARED_CACHE_SIZE_HALF (SHARED_CACHE_SIZE / 2)
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#define DATA_CACHE_SIZE_HALF (DATA_CACHE_SIZE / 2)
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