556 lines
17 KiB
C++
556 lines
17 KiB
C++
/* libs/pixelflinger/codeflinger/MIPSAssembler.h
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**
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** Copyright 2012, The Android Open Source Project
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**
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** Licensed under the Apache License, Version 2.0 (the "License");
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** you may not use this file except in compliance with the License.
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** You may obtain a copy of the License at
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**
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** http://www.apache.org/licenses/LICENSE-2.0
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**
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** Unless required by applicable law or agreed to in writing, software
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** distributed under the License is distributed on an "AS IS" BASIS,
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** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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** See the License for the specific language governing permissions and
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** limitations under the License.
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*/
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#ifndef ANDROID_MIPSASSEMBLER_H
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#define ANDROID_MIPSASSEMBLER_H
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#include <stdint.h>
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#include <sys/types.h>
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#include "tinyutils/KeyedVector.h"
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#include "tinyutils/Vector.h"
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#include "tinyutils/smartpointer.h"
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#include "ARMAssemblerInterface.h"
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#include "CodeCache.h"
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namespace android {
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class MIPSAssembler; // forward reference
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// this class mimics ARMAssembler interface
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// intent is to translate each ARM instruction to 1 or more MIPS instr
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// implementation calls MIPSAssembler class to generate mips code
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class ArmToMipsAssembler : public ARMAssemblerInterface
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{
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public:
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ArmToMipsAssembler(const sp<Assembly>& assembly,
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char *abuf = 0, int linesz = 0, int instr_count = 0);
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virtual ~ArmToMipsAssembler();
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uint32_t* base() const;
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uint32_t* pc() const;
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void disassemble(const char* name);
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virtual void reset();
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virtual int generate(const char* name);
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virtual int getCodegenArch();
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virtual void prolog();
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virtual void epilog(uint32_t touched);
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virtual void comment(const char* string);
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// -----------------------------------------------------------------------
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// shifters and addressing modes
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// -----------------------------------------------------------------------
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// shifters...
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virtual bool isValidImmediate(uint32_t immed);
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virtual int buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm);
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virtual uint32_t imm(uint32_t immediate);
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virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
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virtual uint32_t reg_rrx(int Rm);
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virtual uint32_t reg_reg(int Rm, int type, int Rs);
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// addressing modes...
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// LDR(B)/STR(B)/PLD
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// (immediate and Rm can be negative, which indicates U=0)
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virtual uint32_t immed12_pre(int32_t immed12, int W=0);
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virtual uint32_t immed12_post(int32_t immed12);
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virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
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virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
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// LDRH/LDRSB/LDRSH/STRH
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// (immediate and Rm can be negative, which indicates U=0)
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virtual uint32_t immed8_pre(int32_t immed8, int W=0);
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virtual uint32_t immed8_post(int32_t immed8);
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virtual uint32_t reg_pre(int Rm, int W=0);
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virtual uint32_t reg_post(int Rm);
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virtual void dataProcessing(int opcode, int cc, int s,
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int Rd, int Rn,
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uint32_t Op2);
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virtual void MLA(int cc, int s,
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int Rd, int Rm, int Rs, int Rn);
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virtual void MUL(int cc, int s,
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int Rd, int Rm, int Rs);
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virtual void UMULL(int cc, int s,
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int RdLo, int RdHi, int Rm, int Rs);
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virtual void UMUAL(int cc, int s,
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int RdLo, int RdHi, int Rm, int Rs);
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virtual void SMULL(int cc, int s,
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int RdLo, int RdHi, int Rm, int Rs);
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virtual void SMUAL(int cc, int s,
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int RdLo, int RdHi, int Rm, int Rs);
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virtual void B(int cc, uint32_t* pc);
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virtual void BL(int cc, uint32_t* pc);
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virtual void BX(int cc, int Rn);
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virtual void label(const char* theLabel);
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virtual void B(int cc, const char* label);
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virtual void BL(int cc, const char* label);
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virtual uint32_t* pcForLabel(const char* label);
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virtual void LDR (int cc, int Rd,
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int Rn, uint32_t offset = 0);
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virtual void LDRB(int cc, int Rd,
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int Rn, uint32_t offset = 0);
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virtual void STR (int cc, int Rd,
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int Rn, uint32_t offset = 0);
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virtual void STRB(int cc, int Rd,
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int Rn, uint32_t offset = 0);
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virtual void LDRH (int cc, int Rd,
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int Rn, uint32_t offset = 0);
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virtual void LDRSB(int cc, int Rd,
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int Rn, uint32_t offset = 0);
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virtual void LDRSH(int cc, int Rd,
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int Rn, uint32_t offset = 0);
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virtual void STRH (int cc, int Rd,
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int Rn, uint32_t offset = 0);
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virtual void LDM(int cc, int dir,
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int Rn, int W, uint32_t reg_list);
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virtual void STM(int cc, int dir,
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int Rn, int W, uint32_t reg_list);
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virtual void SWP(int cc, int Rn, int Rd, int Rm);
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virtual void SWPB(int cc, int Rn, int Rd, int Rm);
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virtual void SWI(int cc, uint32_t comment);
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virtual void PLD(int Rn, uint32_t offset);
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virtual void CLZ(int cc, int Rd, int Rm);
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virtual void QADD(int cc, int Rd, int Rm, int Rn);
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virtual void QDADD(int cc, int Rd, int Rm, int Rn);
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virtual void QSUB(int cc, int Rd, int Rm, int Rn);
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virtual void QDSUB(int cc, int Rd, int Rm, int Rn);
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virtual void SMUL(int cc, int xy,
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int Rd, int Rm, int Rs);
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virtual void SMULW(int cc, int y,
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int Rd, int Rm, int Rs);
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virtual void SMLA(int cc, int xy,
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int Rd, int Rm, int Rs, int Rn);
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virtual void SMLAL(int cc, int xy,
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int RdHi, int RdLo, int Rs, int Rm);
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virtual void SMLAW(int cc, int y,
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int Rd, int Rm, int Rs, int Rn);
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// byte/half word extract...
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virtual void UXTB16(int cc, int Rd, int Rm, int rotate);
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// bit manipulation...
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virtual void UBFX(int cc, int Rd, int Rn, int lsb, int width);
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// this is some crap to share is MIPSAssembler class for debug
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char * mArmDisassemblyBuffer;
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int mArmLineLength;
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int mArmInstrCount;
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int mInum; // current arm instuction number (0..n)
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uint32_t** mArmPC; // array: PC for 1st mips instr of
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// each translated ARM instr
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private:
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ArmToMipsAssembler(const ArmToMipsAssembler& rhs);
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ArmToMipsAssembler& operator = (const ArmToMipsAssembler& rhs);
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void init_conditional_labels(void);
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void protectConditionalOperands(int Rd);
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// reg__tmp set to MIPS AT, reg 1
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int dataProcAdrModes(int op, int& source, bool sign = false, int reg_tmp = 1);
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sp<Assembly> mAssembly;
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MIPSAssembler* mMips;
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enum misc_constants_t {
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ARM_MAX_INSTUCTIONS = 512 // based on ASSEMBLY_SCRATCH_SIZE
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};
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enum {
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SRC_REG = 0,
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SRC_IMM,
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SRC_ERROR = -1
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};
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enum addr_modes {
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// start above the range of legal mips reg #'s (0-31)
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AMODE_REG = 0x20,
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AMODE_IMM, AMODE_REG_IMM, // for data processing
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AMODE_IMM_12_PRE, AMODE_IMM_12_POST, // for load/store
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AMODE_REG_SCALE_PRE, AMODE_IMM_8_PRE,
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AMODE_IMM_8_POST, AMODE_REG_PRE,
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AMODE_UNSUPPORTED
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};
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struct addr_mode_t { // address modes for current ARM instruction
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int reg;
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int stype;
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uint32_t value;
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bool writeback; // writeback the adr reg after modification
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} amode;
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enum cond_types {
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CMP_COND = 1,
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SBIT_COND
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};
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struct cond_mode_t { // conditional-execution info for current ARM instruction
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cond_types type;
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int r1;
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int r2;
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int labelnum;
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char label[100][10];
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} cond;
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};
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// This is the basic MIPS assembler, which just creates the opcodes in memory.
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// All the more complicated work is done in ArmToMipsAssember above.
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class MIPSAssembler
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{
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public:
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MIPSAssembler(const sp<Assembly>& assembly, ArmToMipsAssembler *parent);
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virtual ~MIPSAssembler();
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uint32_t* base() const;
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uint32_t* pc() const;
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void reset();
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void disassemble(const char* name);
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void prolog();
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void epilog(uint32_t touched);
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int generate(const char* name);
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void comment(const char* string);
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void label(const char* string);
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// valid only after generate() has been called
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uint32_t* pcForLabel(const char* label);
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// ------------------------------------------------------------------------
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// MIPSAssemblerInterface...
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// ------------------------------------------------------------------------
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#if 0
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#pragma mark -
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#pragma mark Arithmetic...
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#endif
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void ADDU(int Rd, int Rs, int Rt);
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void ADDIU(int Rt, int Rs, int16_t imm);
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void SUBU(int Rd, int Rs, int Rt);
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void SUBIU(int Rt, int Rs, int16_t imm);
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void NEGU(int Rd, int Rs);
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void MUL(int Rd, int Rs, int Rt);
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void MULT(int Rs, int Rt); // dest is hi,lo
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void MULTU(int Rs, int Rt); // dest is hi,lo
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void MADD(int Rs, int Rt); // hi,lo = hi,lo + Rs * Rt
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void MADDU(int Rs, int Rt); // hi,lo = hi,lo + Rs * Rt
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void MSUB(int Rs, int Rt); // hi,lo = hi,lo - Rs * Rt
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void MSUBU(int Rs, int Rt); // hi,lo = hi,lo - Rs * Rt
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void SEB(int Rd, int Rt); // sign-extend byte (mips32r2)
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void SEH(int Rd, int Rt); // sign-extend half-word (mips32r2)
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#if 0
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#pragma mark -
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#pragma mark Comparisons...
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#endif
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void SLT(int Rd, int Rs, int Rt);
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void SLTI(int Rt, int Rs, int16_t imm);
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void SLTU(int Rd, int Rs, int Rt);
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void SLTIU(int Rt, int Rs, int16_t imm);
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#if 0
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#pragma mark -
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#pragma mark Logical...
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#endif
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void AND(int Rd, int Rs, int Rt);
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void ANDI(int Rd, int Rs, uint16_t imm);
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void OR(int Rd, int Rs, int Rt);
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void ORI(int Rt, int Rs, uint16_t imm);
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void NOR(int Rd, int Rs, int Rt);
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void NOT(int Rd, int Rs);
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void XOR(int Rd, int Rs, int Rt);
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void XORI(int Rt, int Rs, uint16_t imm);
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void SLL(int Rd, int Rt, int shft);
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void SLLV(int Rd, int Rt, int Rs);
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void SRL(int Rd, int Rt, int shft);
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void SRLV(int Rd, int Rt, int Rs);
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void SRA(int Rd, int Rt, int shft);
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void SRAV(int Rd, int Rt, int Rs);
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void ROTR(int Rd, int Rt, int shft); // mips32r2
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void ROTRV(int Rd, int Rt, int Rs); // mips32r2
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void RORsyn(int Rd, int Rs, int Rt); // synthetic: d = s rotated by t
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void RORIsyn(int Rd, int Rt, int rot); // synthetic: d = s rotated by immed
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void CLO(int Rd, int Rs);
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void CLZ(int Rd, int Rs);
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void WSBH(int Rd, int Rt);
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#if 0
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#pragma mark -
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#pragma mark Load/store...
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#endif
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void LW(int Rt, int Rbase, int16_t offset);
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void SW(int Rt, int Rbase, int16_t offset);
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void LB(int Rt, int Rbase, int16_t offset);
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void LBU(int Rt, int Rbase, int16_t offset);
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void SB(int Rt, int Rbase, int16_t offset);
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void LH(int Rt, int Rbase, int16_t offset);
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void LHU(int Rt, int Rbase, int16_t offset);
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void SH(int Rt, int Rbase, int16_t offset);
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void LUI(int Rt, int16_t offset);
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#if 0
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#pragma mark -
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#pragma mark Register moves...
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#endif
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void MOVE(int Rd, int Rs);
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void MOVN(int Rd, int Rs, int Rt);
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void MOVZ(int Rd, int Rs, int Rt);
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void MFHI(int Rd);
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void MFLO(int Rd);
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void MTHI(int Rs);
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void MTLO(int Rs);
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#if 0
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#pragma mark -
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#pragma mark Branch...
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#endif
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void B(const char* label);
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void BEQ(int Rs, int Rt, const char* label);
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void BNE(int Rs, int Rt, const char* label);
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void BGEZ(int Rs, const char* label);
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void BGTZ(int Rs, const char* label);
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void BLEZ(int Rs, const char* label);
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void BLTZ(int Rs, const char* label);
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void JR(int Rs);
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#if 0
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#pragma mark -
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#pragma mark Synthesized Branch...
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#endif
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// synthetic variants of above (using slt & friends)
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void BEQZ(int Rs, const char* label);
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void BNEZ(int Rs, const char* label);
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void BGE(int Rs, int Rt, const char* label);
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void BGEU(int Rs, int Rt, const char* label);
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void BGT(int Rs, int Rt, const char* label);
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void BGTU(int Rs, int Rt, const char* label);
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void BLE(int Rs, int Rt, const char* label);
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void BLEU(int Rs, int Rt, const char* label);
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void BLT(int Rs, int Rt, const char* label);
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void BLTU(int Rs, int Rt, const char* label);
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#if 0
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#pragma mark -
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#pragma mark Misc...
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#endif
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void NOP(void);
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void NOP2(void);
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void UNIMPL(void);
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private:
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void string_detab(char *s);
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void string_pad(char *s, int padded_len);
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ArmToMipsAssembler *mParent;
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sp<Assembly> mAssembly;
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uint32_t* mBase;
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uint32_t* mPC;
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uint32_t* mPrologPC;
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int64_t mDuration;
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#if defined(WITH_LIB_HARDWARE)
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bool mQemuTracing;
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#endif
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struct branch_target_t {
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inline branch_target_t() : label(0), pc(0) { }
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inline branch_target_t(const char* l, uint32_t* p)
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: label(l), pc(p) { }
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const char* label;
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uint32_t* pc;
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};
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Vector<branch_target_t> mBranchTargets;
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KeyedVector< const char*, uint32_t* > mLabels;
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KeyedVector< uint32_t*, const char* > mLabelsInverseMapping;
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KeyedVector< uint32_t*, const char* > mComments;
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// opcode field of all instructions
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enum opcode_field {
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spec_op, regimm_op, j_op, jal_op, // 00
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beq_op, bne_op, blez_op, bgtz_op,
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addi_op, addiu_op, slti_op, sltiu_op, // 08
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andi_op, ori_op, xori_op, lui_op,
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cop0_op, cop1_op, cop2_op, cop1x_op, // 10
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beql_op, bnel_op, blezl_op, bgtzl_op,
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daddi_op, daddiu_op, ldl_op, ldr_op, // 18
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spec2_op, jalx_op, mdmx_op, spec3_op,
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lb_op, lh_op, lwl_op, lw_op, // 20
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lbu_op, lhu_op, lwr_op, lwu_op,
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sb_op, sh_op, swl_op, sw_op, // 28
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sdl_op, sdr_op, swr_op, cache_op,
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ll_op, lwc1_op, lwc2_op, pref_op, // 30
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lld_op, ldc1_op, ldc2_op, ld_op,
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sc_op, swc1_op, swc2_op, rsrv_3b_op, // 38
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scd_op, sdc1_op, sdc2_op, sd_op
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};
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// func field for special opcode
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enum func_spec_op {
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sll_fn, movc_fn, srl_fn, sra_fn, // 00
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sllv_fn, pmon_fn, srlv_fn, srav_fn,
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jr_fn, jalr_fn, movz_fn, movn_fn, // 08
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syscall_fn, break_fn, spim_fn, sync_fn,
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mfhi_fn, mthi_fn, mflo_fn, mtlo_fn, // 10
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dsllv_fn, rsrv_spec_2, dsrlv_fn, dsrav_fn,
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mult_fn, multu_fn, div_fn, divu_fn, // 18
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dmult_fn, dmultu_fn, ddiv_fn, ddivu_fn,
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add_fn, addu_fn, sub_fn, subu_fn, // 20
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and_fn, or_fn, xor_fn, nor_fn,
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rsrv_spec_3, rsrv_spec_4, slt_fn, sltu_fn, // 28
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dadd_fn, daddu_fn, dsub_fn, dsubu_fn,
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tge_fn, tgeu_fn, tlt_fn, tltu_fn, // 30
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teq_fn, rsrv_spec_5, tne_fn, rsrv_spec_6,
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dsll_fn, rsrv_spec_7, dsrl_fn, dsra_fn, // 38
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dsll32_fn, rsrv_spec_8, dsrl32_fn, dsra32_fn
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};
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// func field for spec2 opcode
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enum func_spec2_op {
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madd_fn, maddu_fn, mul_fn, rsrv_spec2_3,
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msub_fn, msubu_fn,
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clz_fn = 0x20, clo_fn,
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dclz_fn = 0x24, dclo_fn,
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sdbbp_fn = 0x3f
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};
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// func field for spec3 opcode
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enum func_spec3_op {
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ext_fn, dextm_fn, dextu_fn, dext_fn,
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ins_fn, dinsm_fn, dinsu_fn, dins_fn,
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bshfl_fn = 0x20,
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dbshfl_fn = 0x24,
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rdhwr_fn = 0x3b
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};
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// sa field for spec3 opcodes, with BSHFL function
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enum func_spec3_bshfl {
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wsbh_fn = 0x02,
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seb_fn = 0x10,
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seh_fn = 0x18
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};
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// rt field of regimm opcodes.
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enum regimm_fn {
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bltz_fn, bgez_fn, bltzl_fn, bgezl_fn,
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rsrv_ri_fn4, rsrv_ri_fn5, rsrv_ri_fn6, rsrv_ri_fn7,
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tgei_fn, tgeiu_fn, tlti_fn, tltiu_fn,
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teqi_fn, rsrv_ri_fn_0d, tnei_fn, rsrv_ri_fn0f,
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bltzal_fn, bgezal_fn, bltzall_fn, bgezall_fn,
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bposge32_fn= 0x1c,
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synci_fn = 0x1f
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};
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// func field for mad opcodes (MIPS IV).
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enum mad_func {
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madd_fp_op = 0x08, msub_fp_op = 0x0a,
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nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
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};
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|
|
|
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enum mips_inst_shifts {
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OP_SHF = 26,
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JTARGET_SHF = 0,
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RS_SHF = 21,
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RT_SHF = 16,
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RD_SHF = 11,
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RE_SHF = 6,
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SA_SHF = RE_SHF, // synonym
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IMM_SHF = 0,
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FUNC_SHF = 0,
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|
|
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// mask values
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MSK_16 = 0xffff,
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|
|
|
|
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CACHEOP_SHF = 18,
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CACHESEL_SHF = 16,
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};
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};
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|
|
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enum mips_regnames {
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|
R_zero = 0,
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R_at, R_v0, R_v1, R_a0, R_a1, R_a2, R_a3,
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R_t0, R_t1, R_t2, R_t3, R_t4, R_t5, R_t6, R_t7,
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R_s0, R_s1, R_s2, R_s3, R_s4, R_s5, R_s6, R_s7,
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R_t8, R_t9, R_k0, R_k1, R_gp, R_sp, R_s8, R_ra,
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R_lr = R_s8,
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|
|
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// arm regs 0-15 are mips regs 2-17 (meaning s0 & s1 are used)
|
|
R_at2 = R_s2, // R_at2 = 18 = s2
|
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R_cmp = R_s3, // R_cmp = 19 = s3
|
|
R_cmp2 = R_s4 // R_cmp2 = 20 = s4
|
|
};
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|
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}; // namespace android
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#endif //ANDROID_MIPSASSEMBLER_H
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