247 lines
9.2 KiB
C++
247 lines
9.2 KiB
C++
/*
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* Copyright (C) 2007 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ANDROID_CUTILS_ATOMIC_H
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#define ANDROID_CUTILS_ATOMIC_H
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#include <stdint.h>
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#include <sys/types.h>
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#include <stdatomic.h>
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#ifndef ANDROID_ATOMIC_INLINE
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#define ANDROID_ATOMIC_INLINE static inline
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#endif
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/*
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* A handful of basic atomic operations.
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* THESE ARE HERE FOR LEGACY REASONS ONLY. AVOID.
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*
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* PREFERRED ALTERNATIVES:
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* - Use C++/C/pthread locks/mutexes whenever there is not a
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* convincing reason to do otherwise. Note that very clever and
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* complicated, but correct, lock-free code is often slower than
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* using locks, especially where nontrivial data structures
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* are involved.
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* - C11 stdatomic.h.
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* - Where supported, C++11 std::atomic<T> .
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*
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* PLEASE STOP READING HERE UNLESS YOU ARE TRYING TO UNDERSTAND
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* OR UPDATE OLD CODE.
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*
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* The "acquire" and "release" terms can be defined intuitively in terms
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* of the placement of memory barriers in a simple lock implementation:
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* - wait until compare-and-swap(lock-is-free --> lock-is-held) succeeds
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* - barrier
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* - [do work]
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* - barrier
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* - store(lock-is-free)
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* In very crude terms, the initial (acquire) barrier prevents any of the
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* "work" from happening before the lock is held, and the later (release)
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* barrier ensures that all of the work happens before the lock is released.
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* (Think of cached writes, cache read-ahead, and instruction reordering
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* around the CAS and store instructions.)
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*
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* The barriers must apply to both the compiler and the CPU. Note it is
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* legal for instructions that occur before an "acquire" barrier to be
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* moved down below it, and for instructions that occur after a "release"
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* barrier to be moved up above it.
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*
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* The ARM-driven implementation we use here is short on subtlety,
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* and actually requests a full barrier from the compiler and the CPU.
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* The only difference between acquire and release is in whether they
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* are issued before or after the atomic operation with which they
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* are associated. To ease the transition to C/C++ atomic intrinsics,
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* you should not rely on this, and instead assume that only the minimal
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* acquire/release protection is provided.
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*
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* NOTE: all int32_t* values are expected to be aligned on 32-bit boundaries.
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* If they are not, atomicity is not guaranteed.
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*/
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ANDROID_ATOMIC_INLINE
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volatile atomic_int_least32_t* to_atomic_int_least32_t(volatile const int32_t* addr) {
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#ifdef __cplusplus
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return reinterpret_cast<volatile atomic_int_least32_t*>(const_cast<volatile int32_t*>(addr));
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#else
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return (volatile atomic_int_least32_t*)addr;
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#endif
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}
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/*
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* Basic arithmetic and bitwise operations. These all provide a
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* barrier with "release" ordering, and return the previous value.
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*
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* These have the same characteristics (e.g. what happens on overflow)
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* as the equivalent non-atomic C operations.
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*/
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ANDROID_ATOMIC_INLINE
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int32_t android_atomic_inc(volatile int32_t* addr)
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{
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volatile atomic_int_least32_t* a = to_atomic_int_least32_t(addr);
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/* Int32_t, if it exists, is the same as int_least32_t. */
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return atomic_fetch_add_explicit(a, 1, memory_order_release);
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}
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ANDROID_ATOMIC_INLINE
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int32_t android_atomic_dec(volatile int32_t* addr)
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{
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volatile atomic_int_least32_t* a = to_atomic_int_least32_t(addr);
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return atomic_fetch_sub_explicit(a, 1, memory_order_release);
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}
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ANDROID_ATOMIC_INLINE
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int32_t android_atomic_add(int32_t value, volatile int32_t* addr)
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{
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volatile atomic_int_least32_t* a = to_atomic_int_least32_t(addr);
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return atomic_fetch_add_explicit(a, value, memory_order_release);
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}
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ANDROID_ATOMIC_INLINE
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int32_t android_atomic_and(int32_t value, volatile int32_t* addr)
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{
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volatile atomic_int_least32_t* a = to_atomic_int_least32_t(addr);
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return atomic_fetch_and_explicit(a, value, memory_order_release);
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}
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ANDROID_ATOMIC_INLINE
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int32_t android_atomic_or(int32_t value, volatile int32_t* addr)
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{
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volatile atomic_int_least32_t* a = to_atomic_int_least32_t(addr);
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return atomic_fetch_or_explicit(a, value, memory_order_release);
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}
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/*
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* Perform an atomic load with "acquire" or "release" ordering.
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*
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* Note that the notion of a "release" ordering for a load does not
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* really fit into the C11 or C++11 memory model. The extra ordering
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* is normally observable only by code using memory_order_relaxed
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* atomics, or data races. In the rare cases in which such ordering
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* is called for, use memory_order_relaxed atomics and a leading
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* atomic_thread_fence (typically with memory_order_acquire,
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* not memory_order_release!) instead. If you do not understand
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* this comment, you are in the vast majority, and should not be
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* using release loads or replacing them with anything other than
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* locks or default sequentially consistent atomics.
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*/
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ANDROID_ATOMIC_INLINE
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int32_t android_atomic_acquire_load(volatile const int32_t* addr)
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{
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volatile atomic_int_least32_t* a = to_atomic_int_least32_t(addr);
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return atomic_load_explicit(a, memory_order_acquire);
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}
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ANDROID_ATOMIC_INLINE
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int32_t android_atomic_release_load(volatile const int32_t* addr)
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{
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volatile atomic_int_least32_t* a = to_atomic_int_least32_t(addr);
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atomic_thread_fence(memory_order_seq_cst);
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/* Any reasonable clients of this interface would probably prefer */
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/* something weaker. But some remaining clients seem to be */
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/* abusing this API in strange ways, e.g. by using it as a fence. */
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/* Thus we are conservative until we can get rid of remaining */
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/* clients (and this function). */
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return atomic_load_explicit(a, memory_order_relaxed);
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}
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/*
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* Perform an atomic store with "acquire" or "release" ordering.
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*
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* Note that the notion of an "acquire" ordering for a store does not
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* really fit into the C11 or C++11 memory model. The extra ordering
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* is normally observable only by code using memory_order_relaxed
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* atomics, or data races. In the rare cases in which such ordering
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* is called for, use memory_order_relaxed atomics and a trailing
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* atomic_thread_fence (typically with memory_order_release,
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* not memory_order_acquire!) instead.
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*/
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ANDROID_ATOMIC_INLINE
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void android_atomic_acquire_store(int32_t value, volatile int32_t* addr)
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{
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volatile atomic_int_least32_t* a = to_atomic_int_least32_t(addr);
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atomic_store_explicit(a, value, memory_order_relaxed);
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atomic_thread_fence(memory_order_seq_cst);
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/* Again overly conservative to accomodate weird clients. */
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}
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ANDROID_ATOMIC_INLINE
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void android_atomic_release_store(int32_t value, volatile int32_t* addr)
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{
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volatile atomic_int_least32_t* a = to_atomic_int_least32_t(addr);
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atomic_store_explicit(a, value, memory_order_release);
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}
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/*
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* Compare-and-set operation with "acquire" or "release" ordering.
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*
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* This returns zero if the new value was successfully stored, which will
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* only happen when *addr == oldvalue.
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*
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* (The return value is inverted from implementations on other platforms,
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* but matches the ARM ldrex/strex result.)
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*
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* Implementations that use the release CAS in a loop may be less efficient
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* than possible, because we re-issue the memory barrier on each iteration.
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*/
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ANDROID_ATOMIC_INLINE
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int android_atomic_acquire_cas(int32_t oldvalue, int32_t newvalue,
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volatile int32_t* addr)
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{
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volatile atomic_int_least32_t* a = to_atomic_int_least32_t(addr);
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return !atomic_compare_exchange_strong_explicit(
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a, &oldvalue, newvalue,
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memory_order_acquire,
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memory_order_acquire);
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}
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ANDROID_ATOMIC_INLINE
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int android_atomic_release_cas(int32_t oldvalue, int32_t newvalue,
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volatile int32_t* addr)
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{
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volatile atomic_int_least32_t* a = to_atomic_int_least32_t(addr);
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return !atomic_compare_exchange_strong_explicit(
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a, &oldvalue, newvalue,
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memory_order_release,
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memory_order_relaxed);
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}
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/*
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* Fence primitives.
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*/
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ANDROID_ATOMIC_INLINE
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void android_compiler_barrier(void)
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{
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__asm__ __volatile__ ("" : : : "memory");
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/* Could probably also be: */
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/* atomic_signal_fence(memory_order_seq_cst); */
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}
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ANDROID_ATOMIC_INLINE
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void android_memory_barrier(void)
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{
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atomic_thread_fence(memory_order_seq_cst);
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}
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/*
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* Aliases for code using an older version of this header. These are now
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* deprecated and should not be used. The definitions will be removed
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* in a future release.
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*/
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#define android_atomic_write android_atomic_release_store
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#define android_atomic_cmpxchg android_atomic_release_cas
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#endif // ANDROID_CUTILS_ATOMIC_H
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