581 lines
16 KiB
C++
581 lines
16 KiB
C++
/* libs/pixelflinger/codeflinger/ARMAssembler.cpp
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**
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** Copyright 2006, The Android Open Source Project
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**
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** Licensed under the Apache License, Version 2.0 (the "License");
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** you may not use this file except in compliance with the License.
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** You may obtain a copy of the License at
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**
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** http://www.apache.org/licenses/LICENSE-2.0
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**
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** Unless required by applicable law or agreed to in writing, software
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** distributed under the License is distributed on an "AS IS" BASIS,
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** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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** See the License for the specific language governing permissions and
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** limitations under the License.
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*/
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#define LOG_TAG "ARMAssembler"
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#include <stdio.h>
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#include <stdlib.h>
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#include <cutils/properties.h>
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#include <log/log.h>
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#include <private/pixelflinger/ggl_context.h>
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#include "ARMAssembler.h"
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#include "CodeCache.h"
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#include "disassem.h"
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// ----------------------------------------------------------------------------
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namespace android {
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// ----------------------------------------------------------------------------
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#if 0
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#pragma mark -
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#pragma mark ARMAssembler...
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#endif
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ARMAssembler::ARMAssembler(const sp<Assembly>& assembly)
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: ARMAssemblerInterface(),
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mAssembly(assembly)
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{
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mBase = mPC = (uint32_t *)assembly->base();
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mDuration = ggl_system_time();
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}
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ARMAssembler::~ARMAssembler()
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{
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}
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uint32_t* ARMAssembler::pc() const
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{
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return mPC;
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}
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uint32_t* ARMAssembler::base() const
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{
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return mBase;
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}
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void ARMAssembler::reset()
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{
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mBase = mPC = (uint32_t *)mAssembly->base();
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mBranchTargets.clear();
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mLabels.clear();
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mLabelsInverseMapping.clear();
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mComments.clear();
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}
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int ARMAssembler::getCodegenArch()
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{
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return CODEGEN_ARCH_ARM;
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}
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// ----------------------------------------------------------------------------
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void ARMAssembler::disassemble(const char* name)
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{
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if (name) {
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printf("%s:\n", name);
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}
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size_t count = pc()-base();
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uint32_t* i = base();
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while (count--) {
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ssize_t label = mLabelsInverseMapping.indexOfKey(i);
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if (label >= 0) {
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printf("%s:\n", mLabelsInverseMapping.valueAt(label));
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}
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ssize_t comment = mComments.indexOfKey(i);
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if (comment >= 0) {
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printf("; %s\n", mComments.valueAt(comment));
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}
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printf("%08x: %08x ", uintptr_t(i), int(i[0]));
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::disassemble((uintptr_t)i);
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i++;
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}
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}
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void ARMAssembler::comment(const char* string)
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{
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mComments.add(mPC, string);
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}
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void ARMAssembler::label(const char* theLabel)
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{
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mLabels.add(theLabel, mPC);
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mLabelsInverseMapping.add(mPC, theLabel);
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}
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void ARMAssembler::B(int cc, const char* label)
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{
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mBranchTargets.add(branch_target_t(label, mPC));
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*mPC++ = (cc<<28) | (0xA<<24) | 0;
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}
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void ARMAssembler::BL(int cc, const char* label)
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{
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mBranchTargets.add(branch_target_t(label, mPC));
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*mPC++ = (cc<<28) | (0xB<<24) | 0;
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}
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#if 0
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#pragma mark -
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#pragma mark Prolog/Epilog & Generate...
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#endif
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void ARMAssembler::prolog()
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{
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// write dummy prolog code
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mPrologPC = mPC;
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STM(AL, FD, SP, 1, LSAVED);
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}
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void ARMAssembler::epilog(uint32_t touched)
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{
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touched &= LSAVED;
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if (touched) {
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// write prolog code
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uint32_t* pc = mPC;
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mPC = mPrologPC;
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STM(AL, FD, SP, 1, touched | LLR);
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mPC = pc;
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// write epilog code
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LDM(AL, FD, SP, 1, touched | LLR);
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BX(AL, LR);
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} else { // heh, no registers to save!
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// write prolog code
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uint32_t* pc = mPC;
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mPC = mPrologPC;
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MOV(AL, 0, R0, R0); // NOP
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mPC = pc;
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// write epilog code
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BX(AL, LR);
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}
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}
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int ARMAssembler::generate(const char* name)
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{
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// fixup all the branches
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size_t count = mBranchTargets.size();
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while (count--) {
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const branch_target_t& bt = mBranchTargets[count];
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uint32_t* target_pc = mLabels.valueFor(bt.label);
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LOG_ALWAYS_FATAL_IF(!target_pc,
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"error resolving branch targets, target_pc is null");
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int32_t offset = int32_t(target_pc - (bt.pc+2));
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*bt.pc |= offset & 0xFFFFFF;
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}
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mAssembly->resize( int(pc()-base())*4 );
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// the instruction cache is flushed by CodeCache
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const int64_t duration = ggl_system_time() - mDuration;
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const char * const format = "generated %s (%d ins) at [%p:%p] in %lld ns\n";
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ALOGI(format, name, int(pc()-base()), base(), pc(), duration);
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char value[PROPERTY_VALUE_MAX];
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property_get("debug.pf.disasm", value, "0");
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if (atoi(value) != 0) {
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printf(format, name, int(pc()-base()), base(), pc(), duration);
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disassemble(name);
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}
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return NO_ERROR;
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}
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uint32_t* ARMAssembler::pcForLabel(const char* label)
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{
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return mLabels.valueFor(label);
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}
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// ----------------------------------------------------------------------------
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#if 0
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#pragma mark -
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#pragma mark Data Processing...
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#endif
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void ARMAssembler::dataProcessing(int opcode, int cc,
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int s, int Rd, int Rn, uint32_t Op2)
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{
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*mPC++ = (cc<<28) | (opcode<<21) | (s<<20) | (Rn<<16) | (Rd<<12) | Op2;
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}
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#if 0
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#pragma mark -
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#pragma mark Multiply...
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#endif
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// multiply...
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void ARMAssembler::MLA(int cc, int s,
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int Rd, int Rm, int Rs, int Rn) {
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if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; }
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LOG_FATAL_IF(Rd==Rm, "MLA(r%u,r%u,r%u,r%u)", Rd,Rm,Rs,Rn);
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*mPC++ = (cc<<28) | (1<<21) | (s<<20) |
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(Rd<<16) | (Rn<<12) | (Rs<<8) | 0x90 | Rm;
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}
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void ARMAssembler::MUL(int cc, int s,
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int Rd, int Rm, int Rs) {
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if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; }
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LOG_FATAL_IF(Rd==Rm, "MUL(r%u,r%u,r%u)", Rd,Rm,Rs);
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*mPC++ = (cc<<28) | (s<<20) | (Rd<<16) | (Rs<<8) | 0x90 | Rm;
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}
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void ARMAssembler::UMULL(int cc, int s,
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int RdLo, int RdHi, int Rm, int Rs) {
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LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
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"UMULL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
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*mPC++ = (cc<<28) | (1<<23) | (s<<20) |
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(RdHi<<16) | (RdLo<<12) | (Rs<<8) | 0x90 | Rm;
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}
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void ARMAssembler::UMUAL(int cc, int s,
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int RdLo, int RdHi, int Rm, int Rs) {
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LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
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"UMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
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*mPC++ = (cc<<28) | (1<<23) | (1<<21) | (s<<20) |
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(RdHi<<16) | (RdLo<<12) | (Rs<<8) | 0x90 | Rm;
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}
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void ARMAssembler::SMULL(int cc, int s,
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int RdLo, int RdHi, int Rm, int Rs) {
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LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
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"SMULL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
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*mPC++ = (cc<<28) | (1<<23) | (1<<22) | (s<<20) |
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(RdHi<<16) | (RdLo<<12) | (Rs<<8) | 0x90 | Rm;
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}
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void ARMAssembler::SMUAL(int cc, int s,
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int RdLo, int RdHi, int Rm, int Rs) {
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LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
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"SMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
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*mPC++ = (cc<<28) | (1<<23) | (1<<22) | (1<<21) | (s<<20) |
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(RdHi<<16) | (RdLo<<12) | (Rs<<8) | 0x90 | Rm;
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}
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#if 0
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#pragma mark -
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#pragma mark Branches...
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#endif
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// branches...
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void ARMAssembler::B(int cc, uint32_t* pc)
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{
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int32_t offset = int32_t(pc - (mPC+2));
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*mPC++ = (cc<<28) | (0xA<<24) | (offset & 0xFFFFFF);
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}
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void ARMAssembler::BL(int cc, uint32_t* pc)
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{
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int32_t offset = int32_t(pc - (mPC+2));
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*mPC++ = (cc<<28) | (0xB<<24) | (offset & 0xFFFFFF);
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}
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void ARMAssembler::BX(int cc, int Rn)
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{
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*mPC++ = (cc<<28) | 0x12FFF10 | Rn;
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}
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#if 0
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#pragma mark -
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#pragma mark Data Transfer...
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#endif
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// data transfert...
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void ARMAssembler::LDR(int cc, int Rd, int Rn, uint32_t offset) {
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*mPC++ = (cc<<28) | (1<<26) | (1<<20) | (Rn<<16) | (Rd<<12) | offset;
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}
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void ARMAssembler::LDRB(int cc, int Rd, int Rn, uint32_t offset) {
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*mPC++ = (cc<<28) | (1<<26) | (1<<22) | (1<<20) | (Rn<<16) | (Rd<<12) | offset;
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}
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void ARMAssembler::STR(int cc, int Rd, int Rn, uint32_t offset) {
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*mPC++ = (cc<<28) | (1<<26) | (Rn<<16) | (Rd<<12) | offset;
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}
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void ARMAssembler::STRB(int cc, int Rd, int Rn, uint32_t offset) {
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*mPC++ = (cc<<28) | (1<<26) | (1<<22) | (Rn<<16) | (Rd<<12) | offset;
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}
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void ARMAssembler::LDRH(int cc, int Rd, int Rn, uint32_t offset) {
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*mPC++ = (cc<<28) | (1<<20) | (Rn<<16) | (Rd<<12) | 0xB0 | offset;
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}
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void ARMAssembler::LDRSB(int cc, int Rd, int Rn, uint32_t offset) {
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*mPC++ = (cc<<28) | (1<<20) | (Rn<<16) | (Rd<<12) | 0xD0 | offset;
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}
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void ARMAssembler::LDRSH(int cc, int Rd, int Rn, uint32_t offset) {
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*mPC++ = (cc<<28) | (1<<20) | (Rn<<16) | (Rd<<12) | 0xF0 | offset;
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}
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void ARMAssembler::STRH(int cc, int Rd, int Rn, uint32_t offset) {
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*mPC++ = (cc<<28) | (Rn<<16) | (Rd<<12) | 0xB0 | offset;
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}
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#if 0
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#pragma mark -
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#pragma mark Block Data Transfer...
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#endif
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// block data transfer...
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void ARMAssembler::LDM(int cc, int dir,
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int Rn, int W, uint32_t reg_list)
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{ // ED FD EA FA IB IA DB DA
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const uint8_t P[8] = { 1, 0, 1, 0, 1, 0, 1, 0 };
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const uint8_t U[8] = { 1, 1, 0, 0, 1, 1, 0, 0 };
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*mPC++ = (cc<<28) | (4<<25) | (uint32_t(P[dir])<<24) |
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(uint32_t(U[dir])<<23) | (1<<20) | (W<<21) | (Rn<<16) | reg_list;
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}
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void ARMAssembler::STM(int cc, int dir,
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int Rn, int W, uint32_t reg_list)
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{ // ED FD EA FA IB IA DB DA
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const uint8_t P[8] = { 0, 1, 0, 1, 1, 0, 1, 0 };
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const uint8_t U[8] = { 0, 0, 1, 1, 1, 1, 0, 0 };
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*mPC++ = (cc<<28) | (4<<25) | (uint32_t(P[dir])<<24) |
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(uint32_t(U[dir])<<23) | (0<<20) | (W<<21) | (Rn<<16) | reg_list;
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}
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#if 0
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#pragma mark -
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#pragma mark Special...
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#endif
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// special...
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void ARMAssembler::SWP(int cc, int Rn, int Rd, int Rm) {
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*mPC++ = (cc<<28) | (2<<23) | (Rn<<16) | (Rd << 12) | 0x90 | Rm;
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}
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void ARMAssembler::SWPB(int cc, int Rn, int Rd, int Rm) {
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*mPC++ = (cc<<28) | (2<<23) | (1<<22) | (Rn<<16) | (Rd << 12) | 0x90 | Rm;
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}
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void ARMAssembler::SWI(int cc, uint32_t comment) {
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*mPC++ = (cc<<28) | (0xF<<24) | comment;
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}
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#if 0
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#pragma mark -
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#pragma mark DSP instructions...
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#endif
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// DSP instructions...
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void ARMAssembler::PLD(int Rn, uint32_t offset) {
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LOG_ALWAYS_FATAL_IF(!((offset&(1<<24)) && !(offset&(1<<21))),
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"PLD only P=1, W=0");
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*mPC++ = 0xF550F000 | (Rn<<16) | offset;
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}
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void ARMAssembler::CLZ(int cc, int Rd, int Rm)
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{
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*mPC++ = (cc<<28) | 0x16F0F10| (Rd<<12) | Rm;
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}
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void ARMAssembler::QADD(int cc, int Rd, int Rm, int Rn)
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{
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*mPC++ = (cc<<28) | 0x1000050 | (Rn<<16) | (Rd<<12) | Rm;
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}
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void ARMAssembler::QDADD(int cc, int Rd, int Rm, int Rn)
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{
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*mPC++ = (cc<<28) | 0x1400050 | (Rn<<16) | (Rd<<12) | Rm;
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}
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void ARMAssembler::QSUB(int cc, int Rd, int Rm, int Rn)
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{
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*mPC++ = (cc<<28) | 0x1200050 | (Rn<<16) | (Rd<<12) | Rm;
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}
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void ARMAssembler::QDSUB(int cc, int Rd, int Rm, int Rn)
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{
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*mPC++ = (cc<<28) | 0x1600050 | (Rn<<16) | (Rd<<12) | Rm;
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}
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void ARMAssembler::SMUL(int cc, int xy,
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int Rd, int Rm, int Rs)
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{
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*mPC++ = (cc<<28) | 0x1600080 | (Rd<<16) | (Rs<<8) | (xy<<4) | Rm;
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}
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void ARMAssembler::SMULW(int cc, int y,
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int Rd, int Rm, int Rs)
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{
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*mPC++ = (cc<<28) | 0x12000A0 | (Rd<<16) | (Rs<<8) | (y<<4) | Rm;
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}
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void ARMAssembler::SMLA(int cc, int xy,
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int Rd, int Rm, int Rs, int Rn)
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{
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*mPC++ = (cc<<28) | 0x1000080 | (Rd<<16) | (Rn<<12) | (Rs<<8) | (xy<<4) | Rm;
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}
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void ARMAssembler::SMLAL(int cc, int xy,
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int RdHi, int RdLo, int Rs, int Rm)
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{
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*mPC++ = (cc<<28) | 0x1400080 | (RdHi<<16) | (RdLo<<12) | (Rs<<8) | (xy<<4) | Rm;
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}
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void ARMAssembler::SMLAW(int cc, int y,
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int Rd, int Rm, int Rs, int Rn)
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{
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*mPC++ = (cc<<28) | 0x1200080 | (Rd<<16) | (Rn<<12) | (Rs<<8) | (y<<4) | Rm;
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}
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#if 0
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#pragma mark -
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#pragma mark Byte/half word extract and extend (ARMv6+ only)...
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#endif
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void ARMAssembler::UXTB16(int cc, int Rd, int Rm, int rotate)
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{
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*mPC++ = (cc<<28) | 0x6CF0070 | (Rd<<12) | ((rotate >> 3) << 10) | Rm;
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}
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#if 0
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#pragma mark -
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#pragma mark Bit manipulation (ARMv7+ only)...
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#endif
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// Bit manipulation (ARMv7+ only)...
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void ARMAssembler::UBFX(int cc, int Rd, int Rn, int lsb, int width)
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{
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*mPC++ = (cc<<28) | 0x7E00000 | ((width-1)<<16) | (Rd<<12) | (lsb<<7) | 0x50 | Rn;
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}
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#if 0
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#pragma mark -
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#pragma mark Addressing modes...
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#endif
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int ARMAssembler::buildImmediate(
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uint32_t immediate, uint32_t& rot, uint32_t& imm)
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{
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rot = 0;
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imm = immediate;
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if (imm > 0x7F) { // skip the easy cases
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while (!(imm&3) || (imm&0xFC000000)) {
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uint32_t newval;
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newval = imm >> 2;
|
|
newval |= (imm&3) << 30;
|
|
imm = newval;
|
|
rot += 2;
|
|
if (rot == 32) {
|
|
rot = 0;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
rot = (16 - (rot>>1)) & 0xF;
|
|
|
|
if (imm>=0x100)
|
|
return -EINVAL;
|
|
|
|
if (((imm>>(rot<<1)) | (imm<<(32-(rot<<1)))) != immediate)
|
|
return -1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
// shifters...
|
|
|
|
bool ARMAssembler::isValidImmediate(uint32_t immediate)
|
|
{
|
|
uint32_t rot, imm;
|
|
return buildImmediate(immediate, rot, imm) == 0;
|
|
}
|
|
|
|
uint32_t ARMAssembler::imm(uint32_t immediate)
|
|
{
|
|
uint32_t rot, imm;
|
|
int err = buildImmediate(immediate, rot, imm);
|
|
|
|
LOG_ALWAYS_FATAL_IF(err==-EINVAL,
|
|
"immediate %08x cannot be encoded",
|
|
immediate);
|
|
|
|
LOG_ALWAYS_FATAL_IF(err,
|
|
"immediate (%08x) encoding bogus!",
|
|
immediate);
|
|
|
|
return (1<<25) | (rot<<8) | imm;
|
|
}
|
|
|
|
uint32_t ARMAssembler::reg_imm(int Rm, int type, uint32_t shift)
|
|
{
|
|
return ((shift&0x1F)<<7) | ((type&0x3)<<5) | (Rm&0xF);
|
|
}
|
|
|
|
uint32_t ARMAssembler::reg_rrx(int Rm)
|
|
{
|
|
return (ROR<<5) | (Rm&0xF);
|
|
}
|
|
|
|
uint32_t ARMAssembler::reg_reg(int Rm, int type, int Rs)
|
|
{
|
|
return ((Rs&0xF)<<8) | ((type&0x3)<<5) | (1<<4) | (Rm&0xF);
|
|
}
|
|
|
|
// addressing modes...
|
|
// LDR(B)/STR(B)/PLD (immediate and Rm can be negative, which indicate U=0)
|
|
uint32_t ARMAssembler::immed12_pre(int32_t immed12, int W)
|
|
{
|
|
LOG_ALWAYS_FATAL_IF(abs(immed12) >= 0x800,
|
|
"LDR(B)/STR(B)/PLD immediate too big (%08x)",
|
|
immed12);
|
|
return (1<<24) | (((uint32_t(immed12)>>31)^1)<<23) |
|
|
((W&1)<<21) | (abs(immed12)&0x7FF);
|
|
}
|
|
|
|
uint32_t ARMAssembler::immed12_post(int32_t immed12)
|
|
{
|
|
LOG_ALWAYS_FATAL_IF(abs(immed12) >= 0x800,
|
|
"LDR(B)/STR(B)/PLD immediate too big (%08x)",
|
|
immed12);
|
|
|
|
return (((uint32_t(immed12)>>31)^1)<<23) | (abs(immed12)&0x7FF);
|
|
}
|
|
|
|
uint32_t ARMAssembler::reg_scale_pre(int Rm, int type,
|
|
uint32_t shift, int W)
|
|
{
|
|
return (1<<25) | (1<<24) |
|
|
(((uint32_t(Rm)>>31)^1)<<23) | ((W&1)<<21) |
|
|
reg_imm(abs(Rm), type, shift);
|
|
}
|
|
|
|
uint32_t ARMAssembler::reg_scale_post(int Rm, int type, uint32_t shift)
|
|
{
|
|
return (1<<25) | (((uint32_t(Rm)>>31)^1)<<23) | reg_imm(abs(Rm), type, shift);
|
|
}
|
|
|
|
// LDRH/LDRSB/LDRSH/STRH (immediate and Rm can be negative, which indicate U=0)
|
|
uint32_t ARMAssembler::immed8_pre(int32_t immed8, int W)
|
|
{
|
|
uint32_t offset = abs(immed8);
|
|
|
|
LOG_ALWAYS_FATAL_IF(abs(immed8) >= 0x100,
|
|
"LDRH/LDRSB/LDRSH/STRH immediate too big (%08x)",
|
|
immed8);
|
|
|
|
return (1<<24) | (1<<22) | (((uint32_t(immed8)>>31)^1)<<23) |
|
|
((W&1)<<21) | (((offset&0xF0)<<4)|(offset&0xF));
|
|
}
|
|
|
|
uint32_t ARMAssembler::immed8_post(int32_t immed8)
|
|
{
|
|
uint32_t offset = abs(immed8);
|
|
|
|
LOG_ALWAYS_FATAL_IF(abs(immed8) >= 0x100,
|
|
"LDRH/LDRSB/LDRSH/STRH immediate too big (%08x)",
|
|
immed8);
|
|
|
|
return (1<<22) | (((uint32_t(immed8)>>31)^1)<<23) |
|
|
(((offset&0xF0)<<4) | (offset&0xF));
|
|
}
|
|
|
|
uint32_t ARMAssembler::reg_pre(int Rm, int W)
|
|
{
|
|
return (1<<24) | (((uint32_t(Rm)>>31)^1)<<23) | ((W&1)<<21) | (abs(Rm)&0xF);
|
|
}
|
|
|
|
uint32_t ARMAssembler::reg_post(int Rm)
|
|
{
|
|
return (((uint32_t(Rm)>>31)^1)<<23) | (abs(Rm)&0xF);
|
|
}
|
|
|
|
}; // namespace android
|
|
|