405 lines
13 KiB
C++
405 lines
13 KiB
C++
/* libs/pixelflinger/codeflinger/MIPS64Assembler.h
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**
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** Copyright 2015, The Android Open Source Project
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**
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** Licensed under the Apache License, Version 2.0 (the "License");
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** you may not use this file except in compliance with the License.
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** You may obtain a copy of the License at
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**
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** http://www.apache.org/licenses/LICENSE-2.0
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**
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** Unless required by applicable law or agreed to in writing, software
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** distributed under the License is distributed on an "AS IS" BASIS,
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** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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** See the License for the specific language governing permissions and
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** limitations under the License.
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*/
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#ifndef ANDROID_MIPS64ASSEMBLER_H
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#define ANDROID_MIPS64ASSEMBLER_H
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#include <stdint.h>
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#include <sys/types.h>
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#include "utils/KeyedVector.h"
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#include "utils/Vector.h"
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#include "tinyutils/smartpointer.h"
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#include "ARMAssemblerInterface.h"
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#include "MIPSAssembler.h"
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#include "CodeCache.h"
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namespace android {
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class MIPS64Assembler; // forward reference
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// this class mimics ARMAssembler interface
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// intent is to translate each ARM instruction to 1 or more MIPS instr
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// implementation calls MIPS64Assembler class to generate mips code
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class ArmToMips64Assembler : public ARMAssemblerInterface
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{
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public:
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ArmToMips64Assembler(const sp<Assembly>& assembly,
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char *abuf = 0, int linesz = 0, int instr_count = 0);
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ArmToMips64Assembler(void* assembly);
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virtual ~ArmToMips64Assembler();
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uint32_t* base() const;
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uint32_t* pc() const;
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void disassemble(const char* name);
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virtual void reset();
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virtual int generate(const char* name);
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virtual int getCodegenArch();
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virtual void prolog();
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virtual void epilog(uint32_t touched);
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virtual void comment(const char* string);
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// for testing purposes
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void fix_branches();
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void set_condition(int mode, int R1, int R2);
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// -----------------------------------------------------------------------
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// shifters and addressing modes
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// -----------------------------------------------------------------------
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// shifters...
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virtual bool isValidImmediate(uint32_t immed);
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virtual int buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm);
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virtual uint32_t imm(uint32_t immediate);
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virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
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virtual uint32_t reg_rrx(int Rm);
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virtual uint32_t reg_reg(int Rm, int type, int Rs);
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// addressing modes...
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// LDR(B)/STR(B)/PLD
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// (immediate and Rm can be negative, which indicates U=0)
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virtual uint32_t immed12_pre(int32_t immed12, int W=0);
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virtual uint32_t immed12_post(int32_t immed12);
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virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
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virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
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// LDRH/LDRSB/LDRSH/STRH
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// (immediate and Rm can be negative, which indicates U=0)
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virtual uint32_t immed8_pre(int32_t immed8, int W=0);
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virtual uint32_t immed8_post(int32_t immed8);
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virtual uint32_t reg_pre(int Rm, int W=0);
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virtual uint32_t reg_post(int Rm);
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virtual void dataProcessing(int opcode, int cc, int s,
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int Rd, int Rn,
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uint32_t Op2);
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virtual void MLA(int cc, int s,
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int Rd, int Rm, int Rs, int Rn);
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virtual void MUL(int cc, int s,
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int Rd, int Rm, int Rs);
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virtual void UMULL(int cc, int s,
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int RdLo, int RdHi, int Rm, int Rs);
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virtual void UMUAL(int cc, int s,
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int RdLo, int RdHi, int Rm, int Rs);
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virtual void SMULL(int cc, int s,
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int RdLo, int RdHi, int Rm, int Rs);
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virtual void SMUAL(int cc, int s,
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int RdLo, int RdHi, int Rm, int Rs);
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virtual void B(int cc, uint32_t* pc);
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virtual void BL(int cc, uint32_t* pc);
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virtual void BX(int cc, int Rn);
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virtual void label(const char* theLabel);
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virtual void B(int cc, const char* label);
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virtual void BL(int cc, const char* label);
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virtual uint32_t* pcForLabel(const char* label);
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virtual void LDR (int cc, int Rd,
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int Rn, uint32_t offset = 0);
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virtual void LDRB(int cc, int Rd,
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int Rn, uint32_t offset = 0);
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virtual void STR (int cc, int Rd,
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int Rn, uint32_t offset = 0);
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virtual void STRB(int cc, int Rd,
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int Rn, uint32_t offset = 0);
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virtual void LDRH (int cc, int Rd,
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int Rn, uint32_t offset = 0);
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virtual void LDRSB(int cc, int Rd,
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int Rn, uint32_t offset = 0);
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virtual void LDRSH(int cc, int Rd,
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int Rn, uint32_t offset = 0);
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virtual void STRH (int cc, int Rd,
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int Rn, uint32_t offset = 0);
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virtual void LDM(int cc, int dir,
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int Rn, int W, uint32_t reg_list);
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virtual void STM(int cc, int dir,
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int Rn, int W, uint32_t reg_list);
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virtual void SWP(int cc, int Rn, int Rd, int Rm);
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virtual void SWPB(int cc, int Rn, int Rd, int Rm);
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virtual void SWI(int cc, uint32_t comment);
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virtual void PLD(int Rn, uint32_t offset);
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virtual void CLZ(int cc, int Rd, int Rm);
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virtual void QADD(int cc, int Rd, int Rm, int Rn);
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virtual void QDADD(int cc, int Rd, int Rm, int Rn);
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virtual void QSUB(int cc, int Rd, int Rm, int Rn);
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virtual void QDSUB(int cc, int Rd, int Rm, int Rn);
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virtual void SMUL(int cc, int xy,
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int Rd, int Rm, int Rs);
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virtual void SMULW(int cc, int y,
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int Rd, int Rm, int Rs);
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virtual void SMLA(int cc, int xy,
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int Rd, int Rm, int Rs, int Rn);
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virtual void SMLAL(int cc, int xy,
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int RdHi, int RdLo, int Rs, int Rm);
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virtual void SMLAW(int cc, int y,
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int Rd, int Rm, int Rs, int Rn);
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// byte/half word extract...
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virtual void UXTB16(int cc, int Rd, int Rm, int rotate);
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// bit manipulation...
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virtual void UBFX(int cc, int Rd, int Rn, int lsb, int width);
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// Address loading/storing/manipulation
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virtual void ADDR_LDR(int cc, int Rd, int Rn, uint32_t offset = __immed12_pre(0));
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virtual void ADDR_STR(int cc, int Rd, int Rn, uint32_t offset = __immed12_pre(0));
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virtual void ADDR_ADD(int cc, int s, int Rd, int Rn, uint32_t Op2);
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virtual void ADDR_SUB(int cc, int s, int Rd, int Rn, uint32_t Op2);
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// this is some crap to share is MIPS64Assembler class for debug
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char * mArmDisassemblyBuffer;
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int mArmLineLength;
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int mArmInstrCount;
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int mInum; // current arm instuction number (0..n)
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uint32_t** mArmPC; // array: PC for 1st mips instr of
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// each translated ARM instr
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private:
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ArmToMips64Assembler(const ArmToMips64Assembler& rhs);
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ArmToMips64Assembler& operator = (const ArmToMips64Assembler& rhs);
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void init_conditional_labels(void);
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void protectConditionalOperands(int Rd);
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// reg__tmp set to MIPS AT, reg 1
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int dataProcAdrModes(int op, int& source, bool sign = false, int reg_tmp = 1);
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sp<Assembly> mAssembly;
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MIPS64Assembler* mMips;
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enum misc_constants_t {
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ARM_MAX_INSTUCTIONS = 512 // based on ASSEMBLY_SCRATCH_SIZE
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};
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enum {
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SRC_REG = 0,
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SRC_IMM,
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SRC_ERROR = -1
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};
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enum addr_modes {
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// start above the range of legal mips reg #'s (0-31)
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AMODE_REG = 0x20,
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AMODE_IMM, AMODE_REG_IMM, // for data processing
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AMODE_IMM_12_PRE, AMODE_IMM_12_POST, // for load/store
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AMODE_REG_SCALE_PRE, AMODE_IMM_8_PRE,
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AMODE_IMM_8_POST, AMODE_REG_PRE,
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AMODE_UNSUPPORTED
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};
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struct addr_mode_t { // address modes for current ARM instruction
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int reg;
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int stype;
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uint32_t value;
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bool writeback; // writeback the adr reg after modification
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} amode;
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enum cond_types {
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CMP_COND = 1,
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SBIT_COND
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};
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struct cond_mode_t { // conditional-execution info for current ARM instruction
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cond_types type;
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int r1;
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int r2;
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int labelnum;
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char label[100][10];
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} cond;
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};
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// This is the basic MIPS64 assembler, which just creates the opcodes in memory.
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// All the more complicated work is done in ArmToMips64Assember above.
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// Inherits MIPSAssembler class, and overrides only MIPS64r6 specific stuff
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class MIPS64Assembler : public MIPSAssembler
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{
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public:
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MIPS64Assembler(const sp<Assembly>& assembly, ArmToMips64Assembler *parent);
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MIPS64Assembler(void* assembly, ArmToMips64Assembler *parent);
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virtual ~MIPS64Assembler();
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virtual void reset();
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virtual void disassemble(const char* name);
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void fix_branches();
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// ------------------------------------------------------------------------
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// MIPS64AssemblerInterface...
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// ------------------------------------------------------------------------
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#if 0
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#pragma mark -
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#pragma mark Arithmetic...
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#endif
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void DADDU(int Rd, int Rs, int Rt);
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void DADDIU(int Rt, int Rs, int16_t imm);
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void DSUBU(int Rd, int Rs, int Rt);
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void DSUBIU(int Rt, int Rs, int16_t imm);
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virtual void MUL(int Rd, int Rs, int Rt);
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void MUH(int Rd, int Rs, int Rt);
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#if 0
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#pragma mark -
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#pragma mark Logical...
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#endif
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virtual void CLO(int Rd, int Rs);
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virtual void CLZ(int Rd, int Rs);
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#if 0
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#pragma mark -
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#pragma mark Load/store...
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#endif
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void LD(int Rt, int Rbase, int16_t offset);
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void SD(int Rt, int Rbase, int16_t offset);
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virtual void LUI(int Rt, int16_t offset);
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#if 0
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#pragma mark -
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#pragma mark Branch...
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#endif
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void JR(int Rs);
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protected:
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ArmToMips64Assembler *mParent;
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// opcode field of all instructions
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enum opcode_field {
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spec_op, regimm_op, j_op, jal_op, // 0x00 - 0x03
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beq_op, bne_op, pop06_op, pop07_op, // 0x04 - 0x07
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pop10_op, addiu_op, slti_op, sltiu_op, // 0x08 - 0x0b
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andi_op, ori_op, xori_op, aui_op, // 0x0c - 0x0f
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cop0_op, cop1_op, cop2_op, rsrv_opc_0, // 0x10 - 0x13
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rsrv_opc_1, rsrv_opc_2, pop26_op, pop27_op, // 0x14 - 0x17
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pop30_op, daddiu_op, rsrv_opc_3, rsrv_opc_4, // 0x18 - 0x1b
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rsrv_opc_5, daui_op, msa_op, spec3_op, // 0x1c - 0x1f
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lb_op, lh_op, rsrv_opc_6, lw_op, // 0x20 - 0x23
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lbu_op, lhu_op, rsrv_opc_7, lwu_op, // 0x24 - 0x27
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sb_op, sh_op, rsrv_opc_8, sw_op, // 0x28 - 0x2b
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rsrv_opc_9, rsrv_opc_10, rsrv_opc_11, rsrv_opc_12, // 0x2c - 0x2f
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rsrv_opc_13, lwc1_op, bc_op, rsrv_opc_14, // 0x2c - 0x2f
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rsrv_opc_15, ldc1_op, pop66_op, ld_op, // 0x30 - 0x33
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rsrv_opc_16, swc1_op, balc_op, pcrel_op, // 0x34 - 0x37
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rsrv_opc_17, sdc1_op, pop76_op, sd_op // 0x38 - 0x3b
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};
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// func field for special opcode
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enum func_spec_op {
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sll_fn, rsrv_spec_0, srl_fn, sra_fn,
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sllv_fn, lsa_fn, srlv_fn, srav_fn,
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rsrv_spec_1, jalr_fn, rsrv_spec_2, rsrv_spec_3,
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syscall_fn, break_fn, sdbbp_fn, sync_fn,
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clz_fn, clo_fn, dclz_fn, dclo_fn,
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dsllv_fn, dlsa_fn, dsrlv_fn, dsrav_fn,
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sop30_fn, sop31_fn, sop32_fn, sop33_fn,
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sop34_fn, sop35_fn, sop36_fn, sop37_fn,
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add_fn, addu_fn, sub_fn, subu_fn,
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and_fn, or_fn, xor_fn, nor_fn,
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rsrv_spec_4, rsrv_spec_5, slt_fn, sltu_fn,
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dadd_fn, daddu_fn, dsub_fn, dsubu_fn,
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tge_fn, tgeu_fn, tlt_fn, tltu_fn,
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teq_fn, seleqz_fn, tne_fn, selnez_fn,
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dsll_fn, rsrv_spec_6, dsrl_fn, dsra_fn,
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dsll32_fn, rsrv_spec_7, dsrl32_fn, dsra32_fn
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};
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// func field for spec3 opcode
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enum func_spec3_op {
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ext_fn, dextm_fn, dextu_fn, dext_fn,
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ins_fn, dinsm_fn, dinsu_fn, dins_fn,
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cachee_fn = 0x1b, sbe_fn, she_fn, sce_fn, swe_fn,
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bshfl_fn, prefe_fn = 0x23, dbshfl_fn, cache_fn, sc_fn, scd_fn,
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lbue_fn, lhue_fn, lbe_fn = 0x2c, lhe_fn, lle_fn, lwe_fn,
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pref_fn = 0x35, ll_fn, lld_fn, rdhwr_fn = 0x3b
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};
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// sa field for spec3 opcodes, with BSHFL function
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enum func_spec3_bshfl {
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bitswap_fn,
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wsbh_fn = 0x02,
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dshd_fn = 0x05,
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seb_fn = 0x10,
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seh_fn = 0x18
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};
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// rt field of regimm opcodes.
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enum regimm_fn {
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bltz_fn, bgez_fn,
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dahi_fn = 0x6,
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nal_fn = 0x10, bal_fn, bltzall_fn, bgezall_fn,
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sigrie_fn = 0x17,
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dati_fn = 0x1e, synci_fn
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};
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enum muldiv_fn {
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mul_fn = 0x02, muh_fn
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};
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enum mips_inst_shifts {
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OP_SHF = 26,
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JTARGET_SHF = 0,
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RS_SHF = 21,
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RT_SHF = 16,
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RD_SHF = 11,
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RE_SHF = 6,
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SA_SHF = RE_SHF, // synonym
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IMM_SHF = 0,
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FUNC_SHF = 0,
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// mask values
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MSK_16 = 0xffff,
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CACHEOP_SHF = 18,
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CACHESEL_SHF = 16,
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};
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};
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}; // namespace android
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#endif //ANDROID_MIPS64ASSEMBLER_H
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