1243 lines
38 KiB
C++
1243 lines
38 KiB
C++
/*
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* Copyright (C) 2013 The Android Open Source Project
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#define LOG_TAG "ArmToAarch64Assembler"
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <cutils/log.h>
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#include <cutils/properties.h>
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#include <private/pixelflinger/ggl_context.h>
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#include "codeflinger/Aarch64Assembler.h"
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#include "codeflinger/CodeCache.h"
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#include "codeflinger/Aarch64Disassembler.h"
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/*
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** --------------------------------------------
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** Support for Aarch64 in GGLAssembler JIT
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** --------------------------------------------
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**
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** Approach
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** - GGLAssembler and associated files are largely un-changed.
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** - A translator class maps ArmAssemblerInterface calls to
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** generate AArch64 instructions.
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**
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** ----------------------
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** ArmToAarch64Assembler
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** ----------------------
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**
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** - Subclassed from ArmAssemblerInterface
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**
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** - Translates each ArmAssemblerInterface call to generate
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** one or more Aarch64 instructions as necessary.
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**
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** - Does not implement ArmAssemblerInterface portions unused by GGLAssembler
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** It calls NOT_IMPLEMENTED() for such cases, which in turn logs
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** a fatal message.
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**
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** - Uses A64_.. series of functions to generate instruction machine code
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** for Aarch64 instructions. These functions also log the instruction
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** to LOG, if AARCH64_ASM_DEBUG define is set to 1
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**
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** - Dumps machine code and eqvt assembly if "debug.pf.disasm" option is set
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** It uses aarch64_disassemble to perform disassembly
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**
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** - Uses register 13 (SP in ARM), 15 (PC in ARM), 16, 17 for storing
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** intermediate results. GGLAssembler does not use SP and PC as these
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** registers are marked as reserved. The temporary registers are not
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** saved/restored on stack as these are caller-saved registers in Aarch64
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**
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** - Uses CSEL instruction to support conditional execution. The result is
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** stored in a temporary register and then copied to the target register
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** if the condition is true.
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**
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** - In the case of conditional data transfer instructions, conditional
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** branch is used to skip over instruction, if the condition is false
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**
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** - Wherever possible, immediate values are transferred to temporary
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** register prior to processing. This simplifies overall implementation
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** as instructions requiring immediate values are converted to
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** move immediate instructions followed by register-register instruction.
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**
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** --------------------------------------------
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** ArmToAarch64Assembler unit test bench
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** --------------------------------------------
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**
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** - Tests ArmToAarch64Assembler interface for all the possible
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** ways in which GGLAssembler uses ArmAssemblerInterface interface.
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**
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** - Uses test jacket (written in assembly) to set the registers,
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** condition flags prior to calling generated instruction. It also
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** copies registers and flags at the end of execution. Caller then
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** checks if generated code performed correct operation based on
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** output registers and flags.
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**
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** - Broadly contains three type of tests, (i) data operation tests
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** (ii) data transfer tests and (iii) LDM/STM tests.
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**
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** ----------------------
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** Aarch64 disassembler
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** ----------------------
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** - This disassembler disassembles only those machine codes which can be
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** generated by ArmToAarch64Assembler. It has a unit testbench which
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** tests all the instructions supported by the disassembler.
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**
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** ------------------------------------------------------------------
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** ARMAssembler/ARMAssemblerInterface/ARMAssemblerProxy changes
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** ------------------------------------------------------------------
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**
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** - In existing code, addresses were being handled as 32 bit values at
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** certain places.
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**
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** - Added a new set of functions for address load/store/manipulation.
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** These are ADDR_LDR, ADDR_STR, ADDR_ADD, ADDR_SUB and they map to
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** default 32 bit implementations in ARMAssemblerInterface.
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**
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** - ArmToAarch64Assembler maps these functions to appropriate 64 bit
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** functions.
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**
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** ----------------------
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** GGLAssembler changes
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** ----------------------
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** - Since ArmToAarch64Assembler can generate 4 Aarch64 instructions for
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** each call in worst case, the memory required is set to 4 times
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** ARM memory
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**
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** - Address load/store/manipulation were changed to use new functions
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** added in the ARMAssemblerInterface.
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**
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*/
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#define NOT_IMPLEMENTED() LOG_FATAL("Arm instruction %s not yet implemented\n", __func__)
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#define AARCH64_ASM_DEBUG 0
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#if AARCH64_ASM_DEBUG
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#define LOG_INSTR(...) ALOGD("\t" __VA_ARGS__)
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#define LOG_LABEL(...) ALOGD(__VA_ARGS__)
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#else
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#define LOG_INSTR(...) ((void)0)
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#define LOG_LABEL(...) ((void)0)
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#endif
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namespace android {
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static const char* shift_codes[] =
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{
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"LSL", "LSR", "ASR", "ROR"
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};
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static const char *cc_codes[] =
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{
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"EQ", "NE", "CS", "CC", "MI",
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"PL", "VS", "VC", "HI", "LS",
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"GE", "LT", "GT", "LE", "AL", "NV"
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};
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ArmToAarch64Assembler::ArmToAarch64Assembler(const sp<Assembly>& assembly)
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: ARMAssemblerInterface(),
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mAssembly(assembly)
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{
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mBase = mPC = (uint32_t *)assembly->base();
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mDuration = ggl_system_time();
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mZeroReg = 13;
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mTmpReg1 = 15;
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mTmpReg2 = 16;
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mTmpReg3 = 17;
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}
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ArmToAarch64Assembler::ArmToAarch64Assembler(void *base)
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: ARMAssemblerInterface(), mAssembly(NULL)
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{
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mBase = mPC = (uint32_t *)base;
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mDuration = ggl_system_time();
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// Regs 13, 15, 16, 17 are used as temporary registers
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mZeroReg = 13;
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mTmpReg1 = 15;
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mTmpReg2 = 16;
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mTmpReg3 = 17;
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}
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ArmToAarch64Assembler::~ArmToAarch64Assembler()
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{
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}
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uint32_t* ArmToAarch64Assembler::pc() const
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{
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return mPC;
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}
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uint32_t* ArmToAarch64Assembler::base() const
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{
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return mBase;
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}
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void ArmToAarch64Assembler::reset()
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{
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if(mAssembly == NULL)
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mPC = mBase;
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else
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mBase = mPC = (uint32_t *)mAssembly->base();
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mBranchTargets.clear();
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mLabels.clear();
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mLabelsInverseMapping.clear();
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mComments.clear();
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#if AARCH64_ASM_DEBUG
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ALOGI("RESET\n");
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#endif
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}
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int ArmToAarch64Assembler::getCodegenArch()
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{
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return CODEGEN_ARCH_AARCH64;
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}
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// ----------------------------------------------------------------------------
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void ArmToAarch64Assembler::disassemble(const char* name)
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{
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if(name)
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{
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printf("%s:\n", name);
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}
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size_t count = pc()-base();
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uint32_t* i = base();
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while (count--)
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{
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ssize_t label = mLabelsInverseMapping.indexOfKey(i);
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if (label >= 0)
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{
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printf("%s:\n", mLabelsInverseMapping.valueAt(label));
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}
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ssize_t comment = mComments.indexOfKey(i);
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if (comment >= 0)
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{
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printf("; %s\n", mComments.valueAt(comment));
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}
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printf("%p: %08x ", i, uint32_t(i[0]));
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{
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char instr[256];
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::aarch64_disassemble(*i, instr);
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printf("%s\n", instr);
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}
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i++;
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}
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}
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void ArmToAarch64Assembler::comment(const char* string)
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{
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mComments.add(mPC, string);
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LOG_INSTR("//%s\n", string);
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}
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void ArmToAarch64Assembler::label(const char* theLabel)
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{
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mLabels.add(theLabel, mPC);
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mLabelsInverseMapping.add(mPC, theLabel);
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LOG_LABEL("%s:\n", theLabel);
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}
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void ArmToAarch64Assembler::B(int cc, const char* label)
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{
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mBranchTargets.add(branch_target_t(label, mPC));
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LOG_INSTR("B%s %s\n", cc_codes[cc], label );
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*mPC++ = (0x54 << 24) | cc;
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}
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void ArmToAarch64Assembler::BL(int cc, const char* label)
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{
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NOT_IMPLEMENTED(); //Not Required
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}
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// ----------------------------------------------------------------------------
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//Prolog/Epilog & Generate...
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// ----------------------------------------------------------------------------
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void ArmToAarch64Assembler::prolog()
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{
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// write prolog code
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mPrologPC = mPC;
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*mPC++ = A64_MOVZ_X(mZeroReg,0,0);
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}
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void ArmToAarch64Assembler::epilog(uint32_t touched)
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{
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// write epilog code
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static const int XLR = 30;
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*mPC++ = A64_RET(XLR);
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}
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int ArmToAarch64Assembler::generate(const char* name)
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{
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// fixup all the branches
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size_t count = mBranchTargets.size();
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while (count--)
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{
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const branch_target_t& bt = mBranchTargets[count];
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uint32_t* target_pc = mLabels.valueFor(bt.label);
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LOG_ALWAYS_FATAL_IF(!target_pc,
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"error resolving branch targets, target_pc is null");
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int32_t offset = int32_t(target_pc - bt.pc);
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*bt.pc |= (offset & 0x7FFFF) << 5;
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}
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if(mAssembly != NULL)
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mAssembly->resize( int(pc()-base())*4 );
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// the instruction cache is flushed by CodeCache
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const int64_t duration = ggl_system_time() - mDuration;
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const char * const format = "generated %s (%d ins) at [%p:%p] in %ld ns\n";
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ALOGI(format, name, int(pc()-base()), base(), pc(), duration);
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char value[PROPERTY_VALUE_MAX];
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property_get("debug.pf.disasm", value, "0");
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if (atoi(value) != 0)
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{
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printf(format, name, int(pc()-base()), base(), pc(), duration);
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disassemble(name);
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}
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return NO_ERROR;
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}
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uint32_t* ArmToAarch64Assembler::pcForLabel(const char* label)
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{
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return mLabels.valueFor(label);
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}
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// ----------------------------------------------------------------------------
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// Data Processing...
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// ----------------------------------------------------------------------------
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void ArmToAarch64Assembler::dataProcessingCommon(int opcode,
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int s, int Rd, int Rn, uint32_t Op2)
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{
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if(opcode != opSUB && s == 1)
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{
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NOT_IMPLEMENTED(); //Not required
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return;
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}
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if(opcode != opSUB && opcode != opADD && opcode != opAND &&
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opcode != opORR && opcode != opMVN)
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{
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NOT_IMPLEMENTED(); //Not required
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return;
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}
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if(Op2 == OPERAND_REG_IMM && mAddrMode.reg_imm_shift > 31)
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{
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NOT_IMPLEMENTED();
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return;
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}
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//Store immediate in temporary register and convert
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//immediate operation into register operation
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if(Op2 == OPERAND_IMM)
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{
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int imm = mAddrMode.immediate;
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*mPC++ = A64_MOVZ_W(mTmpReg2, imm & 0x0000FFFF, 0);
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*mPC++ = A64_MOVK_W(mTmpReg2, (imm >> 16) & 0x0000FFFF, 16);
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Op2 = mTmpReg2;
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}
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{
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uint32_t shift;
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uint32_t amount;
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uint32_t Rm;
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if(Op2 == OPERAND_REG_IMM)
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{
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shift = mAddrMode.reg_imm_type;
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amount = mAddrMode.reg_imm_shift;
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Rm = mAddrMode.reg_imm_Rm;
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}
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else if(Op2 < OPERAND_REG)
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{
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shift = 0;
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amount = 0;
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Rm = Op2;
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}
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else
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{
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NOT_IMPLEMENTED(); //Not required
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return;
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}
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switch(opcode)
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{
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case opADD: *mPC++ = A64_ADD_W(Rd, Rn, Rm, shift, amount); break;
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case opAND: *mPC++ = A64_AND_W(Rd, Rn, Rm, shift, amount); break;
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case opORR: *mPC++ = A64_ORR_W(Rd, Rn, Rm, shift, amount); break;
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case opMVN: *mPC++ = A64_ORN_W(Rd, Rn, Rm, shift, amount); break;
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case opSUB: *mPC++ = A64_SUB_W(Rd, Rn, Rm, shift, amount, s);break;
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};
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}
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}
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void ArmToAarch64Assembler::dataProcessing(int opcode, int cc,
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int s, int Rd, int Rn, uint32_t Op2)
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{
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uint32_t Wd;
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if(cc != AL)
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Wd = mTmpReg1;
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else
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Wd = Rd;
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if(opcode == opADD || opcode == opAND || opcode == opORR ||opcode == opSUB)
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{
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dataProcessingCommon(opcode, s, Wd, Rn, Op2);
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}
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else if(opcode == opCMP)
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{
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dataProcessingCommon(opSUB, 1, mTmpReg3, Rn, Op2);
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}
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else if(opcode == opRSB)
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{
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dataProcessingCommon(opSUB, s, Wd, Rn, Op2);
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dataProcessingCommon(opSUB, s, Wd, mZeroReg, Wd);
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}
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else if(opcode == opMOV)
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{
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dataProcessingCommon(opORR, 0, Wd, mZeroReg, Op2);
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if(s == 1)
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{
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dataProcessingCommon(opSUB, 1, mTmpReg3, Wd, mZeroReg);
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}
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}
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else if(opcode == opMVN)
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{
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dataProcessingCommon(opMVN, s, Wd, mZeroReg, Op2);
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}
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else if(opcode == opBIC)
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{
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dataProcessingCommon(opMVN, s, mTmpReg3, mZeroReg, Op2);
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dataProcessingCommon(opAND, s, Wd, Rn, mTmpReg3);
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}
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else
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{
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NOT_IMPLEMENTED();
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return;
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}
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if(cc != AL)
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{
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*mPC++ = A64_CSEL_W(Rd, mTmpReg1, Rd, cc);
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}
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}
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// ----------------------------------------------------------------------------
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// Address Processing...
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// ----------------------------------------------------------------------------
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void ArmToAarch64Assembler::ADDR_ADD(int cc,
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int s, int Rd, int Rn, uint32_t Op2)
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{
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if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
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if(s != 0) { NOT_IMPLEMENTED(); return;} //Not required
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|
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if(Op2 == OPERAND_REG_IMM && mAddrMode.reg_imm_type == LSL)
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{
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int Rm = mAddrMode.reg_imm_Rm;
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int amount = mAddrMode.reg_imm_shift;
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*mPC++ = A64_ADD_X_Wm_SXTW(Rd, Rn, Rm, amount);
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}
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else if(Op2 < OPERAND_REG)
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{
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int Rm = Op2;
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int amount = 0;
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*mPC++ = A64_ADD_X_Wm_SXTW(Rd, Rn, Rm, amount);
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}
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else if(Op2 == OPERAND_IMM)
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{
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int imm = mAddrMode.immediate;
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*mPC++ = A64_MOVZ_W(mTmpReg1, imm & 0x0000FFFF, 0);
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*mPC++ = A64_MOVK_W(mTmpReg1, (imm >> 16) & 0x0000FFFF, 16);
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int Rm = mTmpReg1;
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int amount = 0;
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*mPC++ = A64_ADD_X_Wm_SXTW(Rd, Rn, Rm, amount);
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}
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else
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{
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NOT_IMPLEMENTED(); //Not required
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}
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}
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void ArmToAarch64Assembler::ADDR_SUB(int cc,
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int s, int Rd, int Rn, uint32_t Op2)
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{
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if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
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if(s != 0) { NOT_IMPLEMENTED(); return;} //Not required
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if(Op2 == OPERAND_REG_IMM && mAddrMode.reg_imm_type == LSR)
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{
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*mPC++ = A64_ADD_W(mTmpReg1, mZeroReg, mAddrMode.reg_imm_Rm,
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LSR, mAddrMode.reg_imm_shift);
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*mPC++ = A64_SUB_X_Wm_SXTW(Rd, Rn, mTmpReg1, 0);
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}
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else
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{
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NOT_IMPLEMENTED(); //Not required
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|
}
|
|
}
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// multiply...
|
|
// ----------------------------------------------------------------------------
|
|
void ArmToAarch64Assembler::MLA(int cc, int s,int Rd, int Rm, int Rs, int Rn)
|
|
{
|
|
if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
|
|
|
|
*mPC++ = A64_MADD_W(Rd, Rm, Rs, Rn);
|
|
if(s == 1)
|
|
dataProcessingCommon(opSUB, 1, mTmpReg1, Rd, mZeroReg);
|
|
}
|
|
void ArmToAarch64Assembler::MUL(int cc, int s, int Rd, int Rm, int Rs)
|
|
{
|
|
if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
|
|
if(s != 0) { NOT_IMPLEMENTED(); return;} //Not required
|
|
*mPC++ = A64_MADD_W(Rd, Rm, Rs, mZeroReg);
|
|
}
|
|
void ArmToAarch64Assembler::UMULL(int cc, int s,
|
|
int RdLo, int RdHi, int Rm, int Rs)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
}
|
|
void ArmToAarch64Assembler::UMUAL(int cc, int s,
|
|
int RdLo, int RdHi, int Rm, int Rs)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
}
|
|
void ArmToAarch64Assembler::SMULL(int cc, int s,
|
|
int RdLo, int RdHi, int Rm, int Rs)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
}
|
|
void ArmToAarch64Assembler::SMUAL(int cc, int s,
|
|
int RdLo, int RdHi, int Rm, int Rs)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
}
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// branches relative to PC...
|
|
// ----------------------------------------------------------------------------
|
|
void ArmToAarch64Assembler::B(int cc, uint32_t* pc){
|
|
NOT_IMPLEMENTED(); //Not required
|
|
}
|
|
|
|
void ArmToAarch64Assembler::BL(int cc, uint32_t* pc){
|
|
NOT_IMPLEMENTED(); //Not required
|
|
}
|
|
|
|
void ArmToAarch64Assembler::BX(int cc, int Rn){
|
|
NOT_IMPLEMENTED(); //Not required
|
|
}
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// data transfer...
|
|
// ----------------------------------------------------------------------------
|
|
enum dataTransferOp
|
|
{
|
|
opLDR,opLDRB,opLDRH,opSTR,opSTRB,opSTRH
|
|
};
|
|
|
|
void ArmToAarch64Assembler::dataTransfer(int op, int cc,
|
|
int Rd, int Rn, uint32_t op_type, uint32_t size)
|
|
{
|
|
const int XSP = 31;
|
|
if(Rn == SP)
|
|
Rn = XSP;
|
|
|
|
if(op_type == OPERAND_IMM)
|
|
{
|
|
int addrReg;
|
|
int imm = mAddrMode.immediate;
|
|
if(imm >= 0 && imm < (1<<12))
|
|
*mPC++ = A64_ADD_IMM_X(mTmpReg1, mZeroReg, imm, 0);
|
|
else if(imm < 0 && -imm < (1<<12))
|
|
*mPC++ = A64_SUB_IMM_X(mTmpReg1, mZeroReg, -imm, 0);
|
|
else
|
|
{
|
|
NOT_IMPLEMENTED();
|
|
return;
|
|
}
|
|
|
|
addrReg = Rn;
|
|
if(mAddrMode.preindex == true || mAddrMode.postindex == true)
|
|
{
|
|
*mPC++ = A64_ADD_X(mTmpReg2, addrReg, mTmpReg1);
|
|
if(mAddrMode.preindex == true)
|
|
addrReg = mTmpReg2;
|
|
}
|
|
|
|
if(cc != AL)
|
|
*mPC++ = A64_B_COND(cc^1, 8);
|
|
|
|
*mPC++ = A64_LDRSTR_Wm_SXTW_0(op, size, Rd, addrReg, mZeroReg);
|
|
|
|
if(mAddrMode.writeback == true)
|
|
*mPC++ = A64_CSEL_X(Rn, mTmpReg2, Rn, cc);
|
|
}
|
|
else if(op_type == OPERAND_REG_OFFSET)
|
|
{
|
|
if(cc != AL)
|
|
*mPC++ = A64_B_COND(cc^1, 8);
|
|
*mPC++ = A64_LDRSTR_Wm_SXTW_0(op, size, Rd, Rn, mAddrMode.reg_offset);
|
|
|
|
}
|
|
else if(op_type > OPERAND_UNSUPPORTED)
|
|
{
|
|
if(cc != AL)
|
|
*mPC++ = A64_B_COND(cc^1, 8);
|
|
*mPC++ = A64_LDRSTR_Wm_SXTW_0(op, size, Rd, Rn, mZeroReg);
|
|
}
|
|
else
|
|
{
|
|
NOT_IMPLEMENTED(); // Not required
|
|
}
|
|
return;
|
|
|
|
}
|
|
void ArmToAarch64Assembler::ADDR_LDR(int cc, int Rd, int Rn, uint32_t op_type)
|
|
{
|
|
return dataTransfer(opLDR, cc, Rd, Rn, op_type, 64);
|
|
}
|
|
void ArmToAarch64Assembler::ADDR_STR(int cc, int Rd, int Rn, uint32_t op_type)
|
|
{
|
|
return dataTransfer(opSTR, cc, Rd, Rn, op_type, 64);
|
|
}
|
|
void ArmToAarch64Assembler::LDR(int cc, int Rd, int Rn, uint32_t op_type)
|
|
{
|
|
return dataTransfer(opLDR, cc, Rd, Rn, op_type);
|
|
}
|
|
void ArmToAarch64Assembler::LDRB(int cc, int Rd, int Rn, uint32_t op_type)
|
|
{
|
|
return dataTransfer(opLDRB, cc, Rd, Rn, op_type);
|
|
}
|
|
void ArmToAarch64Assembler::STR(int cc, int Rd, int Rn, uint32_t op_type)
|
|
{
|
|
return dataTransfer(opSTR, cc, Rd, Rn, op_type);
|
|
}
|
|
|
|
void ArmToAarch64Assembler::STRB(int cc, int Rd, int Rn, uint32_t op_type)
|
|
{
|
|
return dataTransfer(opSTRB, cc, Rd, Rn, op_type);
|
|
}
|
|
|
|
void ArmToAarch64Assembler::LDRH(int cc, int Rd, int Rn, uint32_t op_type)
|
|
{
|
|
return dataTransfer(opLDRH, cc, Rd, Rn, op_type);
|
|
}
|
|
void ArmToAarch64Assembler::LDRSB(int cc, int Rd, int Rn, uint32_t offset)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
}
|
|
void ArmToAarch64Assembler::LDRSH(int cc, int Rd, int Rn, uint32_t offset)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
}
|
|
|
|
void ArmToAarch64Assembler::STRH(int cc, int Rd, int Rn, uint32_t op_type)
|
|
{
|
|
return dataTransfer(opSTRH, cc, Rd, Rn, op_type);
|
|
}
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// block data transfer...
|
|
// ----------------------------------------------------------------------------
|
|
void ArmToAarch64Assembler::LDM(int cc, int dir,
|
|
int Rn, int W, uint32_t reg_list)
|
|
{
|
|
const int XSP = 31;
|
|
if(cc != AL || dir != IA || W == 0 || Rn != SP)
|
|
{
|
|
NOT_IMPLEMENTED();
|
|
return;
|
|
}
|
|
|
|
for(int i = 0; i < 32; ++i)
|
|
{
|
|
if((reg_list & (1 << i)))
|
|
{
|
|
int reg = i;
|
|
int size = 16;
|
|
*mPC++ = A64_LDR_IMM_PostIndex(reg, XSP, size);
|
|
}
|
|
}
|
|
}
|
|
|
|
void ArmToAarch64Assembler::STM(int cc, int dir,
|
|
int Rn, int W, uint32_t reg_list)
|
|
{
|
|
const int XSP = 31;
|
|
if(cc != AL || dir != DB || W == 0 || Rn != SP)
|
|
{
|
|
NOT_IMPLEMENTED();
|
|
return;
|
|
}
|
|
|
|
for(int i = 31; i >= 0; --i)
|
|
{
|
|
if((reg_list & (1 << i)))
|
|
{
|
|
int size = -16;
|
|
int reg = i;
|
|
*mPC++ = A64_STR_IMM_PreIndex(reg, XSP, size);
|
|
}
|
|
}
|
|
}
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// special...
|
|
// ----------------------------------------------------------------------------
|
|
void ArmToAarch64Assembler::SWP(int cc, int Rn, int Rd, int Rm)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
}
|
|
void ArmToAarch64Assembler::SWPB(int cc, int Rn, int Rd, int Rm)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
}
|
|
void ArmToAarch64Assembler::SWI(int cc, uint32_t comment)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
}
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// DSP instructions...
|
|
// ----------------------------------------------------------------------------
|
|
void ArmToAarch64Assembler::PLD(int Rn, uint32_t offset) {
|
|
NOT_IMPLEMENTED(); //Not required
|
|
}
|
|
|
|
void ArmToAarch64Assembler::CLZ(int cc, int Rd, int Rm)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
}
|
|
|
|
void ArmToAarch64Assembler::QADD(int cc, int Rd, int Rm, int Rn)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
}
|
|
|
|
void ArmToAarch64Assembler::QDADD(int cc, int Rd, int Rm, int Rn)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
}
|
|
|
|
void ArmToAarch64Assembler::QSUB(int cc, int Rd, int Rm, int Rn)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
}
|
|
|
|
void ArmToAarch64Assembler::QDSUB(int cc, int Rd, int Rm, int Rn)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
}
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// 16 x 16 multiplication
|
|
// ----------------------------------------------------------------------------
|
|
void ArmToAarch64Assembler::SMUL(int cc, int xy,
|
|
int Rd, int Rm, int Rs)
|
|
{
|
|
if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
|
|
|
|
if (xy & xyTB)
|
|
*mPC++ = A64_SBFM_W(mTmpReg1, Rm, 16, 31);
|
|
else
|
|
*mPC++ = A64_SBFM_W(mTmpReg1, Rm, 0, 15);
|
|
|
|
if (xy & xyBT)
|
|
*mPC++ = A64_SBFM_W(mTmpReg2, Rs, 16, 31);
|
|
else
|
|
*mPC++ = A64_SBFM_W(mTmpReg2, Rs, 0, 15);
|
|
|
|
*mPC++ = A64_MADD_W(Rd,mTmpReg1,mTmpReg2, mZeroReg);
|
|
}
|
|
// ----------------------------------------------------------------------------
|
|
// 32 x 16 multiplication
|
|
// ----------------------------------------------------------------------------
|
|
void ArmToAarch64Assembler::SMULW(int cc, int y, int Rd, int Rm, int Rs)
|
|
{
|
|
if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
|
|
|
|
if (y & yT)
|
|
*mPC++ = A64_SBFM_W(mTmpReg1, Rs, 16, 31);
|
|
else
|
|
*mPC++ = A64_SBFM_W(mTmpReg1, Rs, 0, 15);
|
|
|
|
*mPC++ = A64_SBFM_W(mTmpReg2, Rm, 0, 31);
|
|
*mPC++ = A64_SMADDL(mTmpReg3,mTmpReg1,mTmpReg2, mZeroReg);
|
|
*mPC++ = A64_UBFM_X(Rd,mTmpReg3, 16, 47);
|
|
}
|
|
// ----------------------------------------------------------------------------
|
|
// 16 x 16 multiplication and accumulate
|
|
// ----------------------------------------------------------------------------
|
|
void ArmToAarch64Assembler::SMLA(int cc, int xy, int Rd, int Rm, int Rs, int Rn)
|
|
{
|
|
if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
|
|
if(xy != xyBB) { NOT_IMPLEMENTED(); return;} //Not required
|
|
|
|
*mPC++ = A64_SBFM_W(mTmpReg1, Rm, 0, 15);
|
|
*mPC++ = A64_SBFM_W(mTmpReg2, Rs, 0, 15);
|
|
*mPC++ = A64_MADD_W(Rd, mTmpReg1, mTmpReg2, Rn);
|
|
}
|
|
|
|
void ArmToAarch64Assembler::SMLAL(int cc, int xy,
|
|
int RdHi, int RdLo, int Rs, int Rm)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
return;
|
|
}
|
|
|
|
void ArmToAarch64Assembler::SMLAW(int cc, int y,
|
|
int Rd, int Rm, int Rs, int Rn)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
return;
|
|
}
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Byte/half word extract and extend
|
|
// ----------------------------------------------------------------------------
|
|
void ArmToAarch64Assembler::UXTB16(int cc, int Rd, int Rm, int rotate)
|
|
{
|
|
if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
|
|
|
|
*mPC++ = A64_EXTR_W(mTmpReg1, Rm, Rm, rotate * 8);
|
|
|
|
uint32_t imm = 0x00FF00FF;
|
|
*mPC++ = A64_MOVZ_W(mTmpReg2, imm & 0xFFFF, 0);
|
|
*mPC++ = A64_MOVK_W(mTmpReg2, (imm >> 16) & 0x0000FFFF, 16);
|
|
*mPC++ = A64_AND_W(Rd,mTmpReg1, mTmpReg2);
|
|
}
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Bit manipulation
|
|
// ----------------------------------------------------------------------------
|
|
void ArmToAarch64Assembler::UBFX(int cc, int Rd, int Rn, int lsb, int width)
|
|
{
|
|
if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
|
|
*mPC++ = A64_UBFM_W(Rd, Rn, lsb, lsb + width - 1);
|
|
}
|
|
// ----------------------------------------------------------------------------
|
|
// Shifters...
|
|
// ----------------------------------------------------------------------------
|
|
int ArmToAarch64Assembler::buildImmediate(
|
|
uint32_t immediate, uint32_t& rot, uint32_t& imm)
|
|
{
|
|
rot = 0;
|
|
imm = immediate;
|
|
return 0; // Always true
|
|
}
|
|
|
|
|
|
bool ArmToAarch64Assembler::isValidImmediate(uint32_t immediate)
|
|
{
|
|
uint32_t rot, imm;
|
|
return buildImmediate(immediate, rot, imm) == 0;
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::imm(uint32_t immediate)
|
|
{
|
|
mAddrMode.immediate = immediate;
|
|
mAddrMode.writeback = false;
|
|
mAddrMode.preindex = false;
|
|
mAddrMode.postindex = false;
|
|
return OPERAND_IMM;
|
|
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::reg_imm(int Rm, int type, uint32_t shift)
|
|
{
|
|
mAddrMode.reg_imm_Rm = Rm;
|
|
mAddrMode.reg_imm_type = type;
|
|
mAddrMode.reg_imm_shift = shift;
|
|
return OPERAND_REG_IMM;
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::reg_rrx(int Rm)
|
|
{
|
|
NOT_IMPLEMENTED();
|
|
return OPERAND_UNSUPPORTED;
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::reg_reg(int Rm, int type, int Rs)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
return OPERAND_UNSUPPORTED;
|
|
}
|
|
// ----------------------------------------------------------------------------
|
|
// Addressing modes...
|
|
// ----------------------------------------------------------------------------
|
|
uint32_t ArmToAarch64Assembler::immed12_pre(int32_t immed12, int W)
|
|
{
|
|
mAddrMode.immediate = immed12;
|
|
mAddrMode.writeback = W;
|
|
mAddrMode.preindex = true;
|
|
mAddrMode.postindex = false;
|
|
return OPERAND_IMM;
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::immed12_post(int32_t immed12)
|
|
{
|
|
mAddrMode.immediate = immed12;
|
|
mAddrMode.writeback = true;
|
|
mAddrMode.preindex = false;
|
|
mAddrMode.postindex = true;
|
|
return OPERAND_IMM;
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::reg_scale_pre(int Rm, int type,
|
|
uint32_t shift, int W)
|
|
{
|
|
if(type != 0 || shift != 0 || W != 0)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
return OPERAND_UNSUPPORTED;
|
|
}
|
|
else
|
|
{
|
|
mAddrMode.reg_offset = Rm;
|
|
return OPERAND_REG_OFFSET;
|
|
}
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::reg_scale_post(int Rm, int type, uint32_t shift)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
return OPERAND_UNSUPPORTED;
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::immed8_pre(int32_t immed8, int W)
|
|
{
|
|
mAddrMode.immediate = immed8;
|
|
mAddrMode.writeback = W;
|
|
mAddrMode.preindex = true;
|
|
mAddrMode.postindex = false;
|
|
return OPERAND_IMM;
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::immed8_post(int32_t immed8)
|
|
{
|
|
mAddrMode.immediate = immed8;
|
|
mAddrMode.writeback = true;
|
|
mAddrMode.preindex = false;
|
|
mAddrMode.postindex = true;
|
|
return OPERAND_IMM;
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::reg_pre(int Rm, int W)
|
|
{
|
|
if(W != 0)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
return OPERAND_UNSUPPORTED;
|
|
}
|
|
else
|
|
{
|
|
mAddrMode.reg_offset = Rm;
|
|
return OPERAND_REG_OFFSET;
|
|
}
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::reg_post(int Rm)
|
|
{
|
|
NOT_IMPLEMENTED(); //Not required
|
|
return OPERAND_UNSUPPORTED;
|
|
}
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// A64 instructions
|
|
// ----------------------------------------------------------------------------
|
|
|
|
static const char * dataTransferOpName[] =
|
|
{
|
|
"LDR","LDRB","LDRH","STR","STRB","STRH"
|
|
};
|
|
|
|
static const uint32_t dataTransferOpCode [] =
|
|
{
|
|
((0xB8u << 24) | (0x3 << 21) | (0x6 << 13) | (0x0 << 12) |(0x1 << 11)),
|
|
((0x38u << 24) | (0x3 << 21) | (0x6 << 13) | (0x1 << 12) |(0x1 << 11)),
|
|
((0x78u << 24) | (0x3 << 21) | (0x6 << 13) | (0x0 << 12) |(0x1 << 11)),
|
|
((0xB8u << 24) | (0x1 << 21) | (0x6 << 13) | (0x0 << 12) |(0x1 << 11)),
|
|
((0x38u << 24) | (0x1 << 21) | (0x6 << 13) | (0x1 << 12) |(0x1 << 11)),
|
|
((0x78u << 24) | (0x1 << 21) | (0x6 << 13) | (0x0 << 12) |(0x1 << 11))
|
|
};
|
|
uint32_t ArmToAarch64Assembler::A64_LDRSTR_Wm_SXTW_0(uint32_t op,
|
|
uint32_t size, uint32_t Rt,
|
|
uint32_t Rn, uint32_t Rm)
|
|
{
|
|
if(size == 32)
|
|
{
|
|
LOG_INSTR("%s W%d, [X%d, W%d, SXTW #0]\n",
|
|
dataTransferOpName[op], Rt, Rn, Rm);
|
|
return(dataTransferOpCode[op] | (Rm << 16) | (Rn << 5) | Rt);
|
|
}
|
|
else
|
|
{
|
|
LOG_INSTR("%s X%d, [X%d, W%d, SXTW #0]\n",
|
|
dataTransferOpName[op], Rt, Rn, Rm);
|
|
return(dataTransferOpCode[op] | (0x1<<30) | (Rm<<16) | (Rn<<5)|Rt);
|
|
}
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_STR_IMM_PreIndex(uint32_t Rt,
|
|
uint32_t Rn, int32_t simm)
|
|
{
|
|
if(Rn == 31)
|
|
LOG_INSTR("STR W%d, [SP, #%d]!\n", Rt, simm);
|
|
else
|
|
LOG_INSTR("STR W%d, [X%d, #%d]!\n", Rt, Rn, simm);
|
|
|
|
uint32_t imm9 = (unsigned)(simm) & 0x01FF;
|
|
return (0xB8 << 24) | (imm9 << 12) | (0x3 << 10) | (Rn << 5) | Rt;
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_LDR_IMM_PostIndex(uint32_t Rt,
|
|
uint32_t Rn, int32_t simm)
|
|
{
|
|
if(Rn == 31)
|
|
LOG_INSTR("LDR W%d, [SP], #%d\n",Rt,simm);
|
|
else
|
|
LOG_INSTR("LDR W%d, [X%d], #%d\n",Rt, Rn, simm);
|
|
|
|
uint32_t imm9 = (unsigned)(simm) & 0x01FF;
|
|
return (0xB8 << 24) | (0x1 << 22) |
|
|
(imm9 << 12) | (0x1 << 10) | (Rn << 5) | Rt;
|
|
|
|
}
|
|
uint32_t ArmToAarch64Assembler::A64_ADD_X_Wm_SXTW(uint32_t Rd,
|
|
uint32_t Rn,
|
|
uint32_t Rm,
|
|
uint32_t amount)
|
|
{
|
|
LOG_INSTR("ADD X%d, X%d, W%d, SXTW #%d\n", Rd, Rn, Rm, amount);
|
|
return ((0x8B << 24) | (0x1 << 21) |(Rm << 16) |
|
|
(0x6 << 13) | (amount << 10) | (Rn << 5) | Rd);
|
|
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_SUB_X_Wm_SXTW(uint32_t Rd,
|
|
uint32_t Rn,
|
|
uint32_t Rm,
|
|
uint32_t amount)
|
|
{
|
|
LOG_INSTR("SUB X%d, X%d, W%d, SXTW #%d\n", Rd, Rn, Rm, amount);
|
|
return ((0xCB << 24) | (0x1 << 21) |(Rm << 16) |
|
|
(0x6 << 13) | (amount << 10) | (Rn << 5) | Rd);
|
|
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_B_COND(uint32_t cc, uint32_t offset)
|
|
{
|
|
LOG_INSTR("B.%s #.+%d\n", cc_codes[cc], offset);
|
|
return (0x54 << 24) | ((offset/4) << 5) | (cc);
|
|
|
|
}
|
|
uint32_t ArmToAarch64Assembler::A64_ADD_X(uint32_t Rd, uint32_t Rn,
|
|
uint32_t Rm, uint32_t shift,
|
|
uint32_t amount)
|
|
{
|
|
LOG_INSTR("ADD X%d, X%d, X%d, %s #%d\n",
|
|
Rd, Rn, Rm, shift_codes[shift], amount);
|
|
return ((0x8B << 24) | (shift << 22) | ( Rm << 16) |
|
|
(amount << 10) |(Rn << 5) | Rd);
|
|
}
|
|
uint32_t ArmToAarch64Assembler::A64_ADD_IMM_X(uint32_t Rd, uint32_t Rn,
|
|
uint32_t imm, uint32_t shift)
|
|
{
|
|
LOG_INSTR("ADD X%d, X%d, #%d, LSL #%d\n", Rd, Rn, imm, shift);
|
|
return (0x91 << 24) | ((shift/12) << 22) | (imm << 10) | (Rn << 5) | Rd;
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_SUB_IMM_X(uint32_t Rd, uint32_t Rn,
|
|
uint32_t imm, uint32_t shift)
|
|
{
|
|
LOG_INSTR("SUB X%d, X%d, #%d, LSL #%d\n", Rd, Rn, imm, shift);
|
|
return (0xD1 << 24) | ((shift/12) << 22) | (imm << 10) | (Rn << 5) | Rd;
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_ADD_W(uint32_t Rd, uint32_t Rn,
|
|
uint32_t Rm, uint32_t shift,
|
|
uint32_t amount)
|
|
{
|
|
LOG_INSTR("ADD W%d, W%d, W%d, %s #%d\n",
|
|
Rd, Rn, Rm, shift_codes[shift], amount);
|
|
return ((0x0B << 24) | (shift << 22) | ( Rm << 16) |
|
|
(amount << 10) |(Rn << 5) | Rd);
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_SUB_W(uint32_t Rd, uint32_t Rn,
|
|
uint32_t Rm, uint32_t shift,
|
|
uint32_t amount,
|
|
uint32_t setflag)
|
|
{
|
|
if(setflag == 0)
|
|
{
|
|
LOG_INSTR("SUB W%d, W%d, W%d, %s #%d\n",
|
|
Rd, Rn, Rm, shift_codes[shift], amount);
|
|
return ((0x4B << 24) | (shift << 22) | ( Rm << 16) |
|
|
(amount << 10) |(Rn << 5) | Rd);
|
|
}
|
|
else
|
|
{
|
|
LOG_INSTR("SUBS W%d, W%d, W%d, %s #%d\n",
|
|
Rd, Rn, Rm, shift_codes[shift], amount);
|
|
return ((0x6B << 24) | (shift << 22) | ( Rm << 16) |
|
|
(amount << 10) |(Rn << 5) | Rd);
|
|
}
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_AND_W(uint32_t Rd, uint32_t Rn,
|
|
uint32_t Rm, uint32_t shift,
|
|
uint32_t amount)
|
|
{
|
|
LOG_INSTR("AND W%d, W%d, W%d, %s #%d\n",
|
|
Rd, Rn, Rm, shift_codes[shift], amount);
|
|
return ((0x0A << 24) | (shift << 22) | ( Rm << 16) |
|
|
(amount << 10) |(Rn << 5) | Rd);
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_ORR_W(uint32_t Rd, uint32_t Rn,
|
|
uint32_t Rm, uint32_t shift,
|
|
uint32_t amount)
|
|
{
|
|
LOG_INSTR("ORR W%d, W%d, W%d, %s #%d\n",
|
|
Rd, Rn, Rm, shift_codes[shift], amount);
|
|
return ((0x2A << 24) | (shift << 22) | ( Rm << 16) |
|
|
(amount << 10) |(Rn << 5) | Rd);
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_ORN_W(uint32_t Rd, uint32_t Rn,
|
|
uint32_t Rm, uint32_t shift,
|
|
uint32_t amount)
|
|
{
|
|
LOG_INSTR("ORN W%d, W%d, W%d, %s #%d\n",
|
|
Rd, Rn, Rm, shift_codes[shift], amount);
|
|
return ((0x2A << 24) | (shift << 22) | (0x1 << 21) | ( Rm << 16) |
|
|
(amount << 10) |(Rn << 5) | Rd);
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_CSEL_X(uint32_t Rd, uint32_t Rn,
|
|
uint32_t Rm, uint32_t cond)
|
|
{
|
|
LOG_INSTR("CSEL X%d, X%d, X%d, %s\n", Rd, Rn, Rm, cc_codes[cond]);
|
|
return ((0x9A << 24)|(0x1 << 23)|(Rm << 16) |(cond << 12)| (Rn << 5) | Rd);
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_CSEL_W(uint32_t Rd, uint32_t Rn,
|
|
uint32_t Rm, uint32_t cond)
|
|
{
|
|
LOG_INSTR("CSEL W%d, W%d, W%d, %s\n", Rd, Rn, Rm, cc_codes[cond]);
|
|
return ((0x1A << 24)|(0x1 << 23)|(Rm << 16) |(cond << 12)| (Rn << 5) | Rd);
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_RET(uint32_t Rn)
|
|
{
|
|
LOG_INSTR("RET X%d\n", Rn);
|
|
return ((0xD6 << 24) | (0x1 << 22) | (0x1F << 16) | (Rn << 5));
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_MOVZ_X(uint32_t Rd, uint32_t imm,
|
|
uint32_t shift)
|
|
{
|
|
LOG_INSTR("MOVZ X%d, #0x%x, LSL #%d\n", Rd, imm, shift);
|
|
return(0xD2 << 24) | (0x1 << 23) | ((shift/16) << 21) | (imm << 5) | Rd;
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_MOVK_W(uint32_t Rd, uint32_t imm,
|
|
uint32_t shift)
|
|
{
|
|
LOG_INSTR("MOVK W%d, #0x%x, LSL #%d\n", Rd, imm, shift);
|
|
return (0x72 << 24) | (0x1 << 23) | ((shift/16) << 21) | (imm << 5) | Rd;
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_MOVZ_W(uint32_t Rd, uint32_t imm,
|
|
uint32_t shift)
|
|
{
|
|
LOG_INSTR("MOVZ W%d, #0x%x, LSL #%d\n", Rd, imm, shift);
|
|
return(0x52 << 24) | (0x1 << 23) | ((shift/16) << 21) | (imm << 5) | Rd;
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_SMADDL(uint32_t Rd, uint32_t Rn,
|
|
uint32_t Rm, uint32_t Ra)
|
|
{
|
|
LOG_INSTR("SMADDL X%d, W%d, W%d, X%d\n",Rd, Rn, Rm, Ra);
|
|
return ((0x9B << 24) | (0x1 << 21) | (Rm << 16)|(Ra << 10)|(Rn << 5) | Rd);
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_MADD_W(uint32_t Rd, uint32_t Rn,
|
|
uint32_t Rm, uint32_t Ra)
|
|
{
|
|
LOG_INSTR("MADD W%d, W%d, W%d, W%d\n",Rd, Rn, Rm, Ra);
|
|
return ((0x1B << 24) | (Rm << 16) | (Ra << 10) |(Rn << 5) | Rd);
|
|
}
|
|
|
|
uint32_t ArmToAarch64Assembler::A64_SBFM_W(uint32_t Rd, uint32_t Rn,
|
|
uint32_t immr, uint32_t imms)
|
|
{
|
|
LOG_INSTR("SBFM W%d, W%d, #%d, #%d\n", Rd, Rn, immr, imms);
|
|
return ((0x13 << 24) | (immr << 16) | (imms << 10) | (Rn << 5) | Rd);
|
|
|
|
}
|
|
uint32_t ArmToAarch64Assembler::A64_UBFM_W(uint32_t Rd, uint32_t Rn,
|
|
uint32_t immr, uint32_t imms)
|
|
{
|
|
LOG_INSTR("UBFM W%d, W%d, #%d, #%d\n", Rd, Rn, immr, imms);
|
|
return ((0x53 << 24) | (immr << 16) | (imms << 10) | (Rn << 5) | Rd);
|
|
|
|
}
|
|
uint32_t ArmToAarch64Assembler::A64_UBFM_X(uint32_t Rd, uint32_t Rn,
|
|
uint32_t immr, uint32_t imms)
|
|
{
|
|
LOG_INSTR("UBFM X%d, X%d, #%d, #%d\n", Rd, Rn, immr, imms);
|
|
return ((0xD3 << 24) | (0x1 << 22) |
|
|
(immr << 16) | (imms << 10) | (Rn << 5) | Rd);
|
|
|
|
}
|
|
uint32_t ArmToAarch64Assembler::A64_EXTR_W(uint32_t Rd, uint32_t Rn,
|
|
uint32_t Rm, uint32_t lsb)
|
|
{
|
|
LOG_INSTR("EXTR W%d, W%d, W%d, #%d\n", Rd, Rn, Rm, lsb);
|
|
return (0x13 << 24)|(0x1 << 23) | (Rm << 16) | (lsb << 10)|(Rn << 5) | Rd;
|
|
}
|
|
|
|
}; // namespace android
|
|
|