260 lines
7.0 KiB
ArmAsm
260 lines
7.0 KiB
ArmAsm
/*
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* Copyright (C) 2005 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <machine/cpu-features.h>
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/*
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* NOTE: these atomic operations are SMP safe on all architectures,
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* except swap(), see below.
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*/
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.text
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.align
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.global android_atomic_write
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.global android_atomic_inc
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.global android_atomic_dec
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.global android_atomic_add
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.global android_atomic_and
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.global android_atomic_or
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.global android_atomic_swap
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.global android_atomic_cmpxchg
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/*
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* ----------------------------------------------------------------------------
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* int __kernel_cmpxchg(int oldval, int newval, int *ptr)
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* clobbered: r3, ip, flags
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* return 0 if a swap was made, non-zero otherwise.
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*/
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.equ kernel_cmpxchg, 0xFFFF0FC0
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.equ kernel_atomic_base, 0xFFFF0FFF
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/*
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* ----------------------------------------------------------------------------
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* android_atomic_write
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* input: r0=value, r1=address
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* output: void
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*/
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android_atomic_write:
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str r0, [r1]
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bx lr;
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/*
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* ----------------------------------------------------------------------------
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* android_atomic_inc
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* input: r0 = address
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* output: r0 = old value
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*/
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android_atomic_inc:
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stmdb sp!, {r4, lr}
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mov r2, r0
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1: @ android_atomic_inc
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ldr r0, [r2]
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mov r3, #kernel_atomic_base
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#ifdef __ARM_HAVE_PC_INTERWORK
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add lr, pc, #4
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add r1, r0, #1
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add pc, r3, #(kernel_cmpxchg - kernel_atomic_base)
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#else
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add r1, r0, #1
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add r3, r3, #(kernel_cmpxchg - kernel_atomic_base)
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mov lr, pc
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bx r3
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#endif
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bcc 1b
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sub r0, r1, #1
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ldmia sp!, {r4, lr}
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bx lr
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/*
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* ----------------------------------------------------------------------------
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* android_atomic_dec
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* input: r0=address
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* output: r0 = old value
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*/
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android_atomic_dec:
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stmdb sp!, {r4, lr}
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mov r2, r0
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1: @ android_atomic_dec
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ldr r0, [r2]
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mov r3, #kernel_atomic_base
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#ifdef __ARM_HAVE_PC_INTERWORK
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add lr, pc, #4
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sub r1, r0, #1
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add pc, r3, #(kernel_cmpxchg - kernel_atomic_base)
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#else
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sub r1, r0, #1
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add r3, r3, #(kernel_cmpxchg - kernel_atomic_base)
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mov lr, pc
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bx r3
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#endif
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bcc 1b
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add r0, r1, #1
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ldmia sp!, {r4, lr}
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bx lr
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/*
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* ----------------------------------------------------------------------------
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* android_atomic_add
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* input: r0=value, r1=address
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* output: r0 = old value
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*/
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android_atomic_add:
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stmdb sp!, {r4, lr}
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mov r2, r1
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mov r4, r0
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1: @ android_atomic_add
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ldr r0, [r2]
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mov r3, #kernel_atomic_base
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#ifdef __ARM_HAVE_PC_INTERWORK
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add lr, pc, #4
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add r1, r0, r4
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add pc, r3, #(kernel_cmpxchg - kernel_atomic_base)
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#else
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add r1, r0, r4
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add r3, r3, #(kernel_cmpxchg - kernel_atomic_base)
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mov lr, pc
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bx r3
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#endif
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bcc 1b
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sub r0, r1, r4
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ldmia sp!, {r4, lr}
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bx lr
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/*
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* ----------------------------------------------------------------------------
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* android_atomic_and
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* input: r0=value, r1=address
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* output: r0 = old value
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*/
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android_atomic_and:
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stmdb sp!, {r4, r5, lr}
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mov r2, r1 /* r2 = address */
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mov r4, r0 /* r4 = the value */
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1: @ android_atomic_and
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ldr r0, [r2] /* r0 = address[0] */
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mov r3, #kernel_atomic_base
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#ifdef __ARM_HAVE_PC_INTERWORK
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add lr, pc, #8
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mov r5, r0 /* r5 = save address[0] */
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and r1, r0, r4 /* r1 = new value */
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add pc, r3, #(kernel_cmpxchg - kernel_atomic_base) /* call cmpxchg() */
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#else
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mov r5, r0 /* r5 = save address[0] */
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and r1, r0, r4 /* r1 = new value */
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add r3, r3, #(kernel_cmpxchg - kernel_atomic_base) /* call cmpxchg() */
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mov lr, pc
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bx r3
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#endif
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bcc 1b
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mov r0, r5
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ldmia sp!, {r4, r5, lr}
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bx lr
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/*
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* ----------------------------------------------------------------------------
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* android_atomic_or
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* input: r0=value, r1=address
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* output: r0 = old value
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*/
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android_atomic_or:
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stmdb sp!, {r4, r5, lr}
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mov r2, r1 /* r2 = address */
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mov r4, r0 /* r4 = the value */
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1: @ android_atomic_or
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ldr r0, [r2] /* r0 = address[0] */
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mov r3, #kernel_atomic_base
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#ifdef __ARM_HAVE_PC_INTERWORK
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add lr, pc, #8
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mov r5, r0 /* r5 = save address[0] */
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orr r1, r0, r4 /* r1 = new value */
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add pc, r3, #(kernel_cmpxchg - kernel_atomic_base) /* call cmpxchg() */
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#else
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mov r5, r0 /* r5 = save address[0] */
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orr r1, r0, r4 /* r1 = new value */
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add r3, r3, #(kernel_cmpxchg - kernel_atomic_base) /* call cmpxchg() */
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mov lr, pc
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bx r3
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#endif
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bcc 1b
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mov r0, r5
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ldmia sp!, {r4, r5, lr}
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bx lr
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/*
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* ----------------------------------------------------------------------------
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* android_atomic_swap
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* input: r0=value, r1=address
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* output: r0 = old value
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*/
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/* FIXME: this is not safe on SMP systems
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* a general way to do it is to use kernel_cmpxchg */
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android_atomic_swap:
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swp r0, r0, [r1]
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bx lr
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/*
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* ----------------------------------------------------------------------------
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* android_atomic_cmpxchg
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* input: r0=oldvalue, r1=newvalue, r2=address
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* output: r0 = 0 (xchg done) or non-zero (xchg not done)
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*/
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android_atomic_cmpxchg:
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stmdb sp!, {r4, lr}
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mov r4, r0 /* r4 = save oldvalue */
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1: @ android_atomic_cmpxchg
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mov r3, #kernel_atomic_base
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#ifdef __ARM_HAVE_PC_INTERWORK
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add lr, pc, #4
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mov r0, r4 /* r0 = oldvalue */
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add pc, r3, #(kernel_cmpxchg - kernel_atomic_base)
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#else
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mov r0, r4 /* r0 = oldvalue */
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add r3, r3, #(kernel_cmpxchg - kernel_atomic_base)
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mov lr, pc
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bx r3
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#endif
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bcs 2f /* swap was made. we're good, return. */
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ldr r3, [r2] /* swap not made, see if it's because *ptr!=oldvalue */
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cmp r3, r4
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beq 1b
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2: @ android_atomic_cmpxchg
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ldmia sp!, {r4, lr}
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bx lr
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/*
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* ----------------------------------------------------------------------------
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* android_atomic_cmpxchg_64
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* input: r0-r1=oldvalue, r2-r3=newvalue, arg4 (on stack)=address
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* output: r0 = 0 (xchg done) or non-zero (xchg not done)
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*/
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/* TODO: NEED IMPLEMENTATION FOR THIS ARCHITECTURE */
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