mirror of https://gitee.com/openkylin/qemu.git
104 lines
3.3 KiB
C
104 lines
3.3 KiB
C
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/*
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* Qemu PowerPC 440 chip emulation
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*
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* Copyright 2007 IBM Corporation.
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* Authors:
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* Jerone Young <jyoung5@us.ibm.com>
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* Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
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* Hollis Blanchard <hollisb@us.ibm.com>
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*
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*/
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#include "hw.h"
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#include "isa.h"
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#include "ppc.h"
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#include "ppc4xx.h"
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#include "ppc440.h"
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#include "ppc405.h"
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#include "sysemu.h"
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#include "kvm.h"
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#define PPC440EP_PCI_CONFIG 0xeec00000
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#define PPC440EP_PCI_INTACK 0xeed00000
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#define PPC440EP_PCI_SPECIAL 0xeed00000
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#define PPC440EP_PCI_REGS 0xef400000
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#define PPC440EP_PCI_IO 0xe8000000
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#define PPC440EP_PCI_IOLEN 0x00010000
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#define PPC440EP_SDRAM_NR_BANKS 4
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static const unsigned int ppc440ep_sdram_bank_sizes[] = {
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256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0
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};
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CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
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const unsigned int pci_irq_nrs[4], int do_init)
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{
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target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
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target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
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CPUState *env;
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ppc4xx_mmio_t *mmio;
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qemu_irq *pic;
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qemu_irq *irqs;
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qemu_irq *pci_irqs;
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env = cpu_ppc_init("440EP");
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if (!env && kvm_enabled()) {
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/* XXX Since qemu doesn't yet emulate 440, we just say it's a 405.
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* Since KVM doesn't use qemu's CPU emulation it seems to be working
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* OK. */
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env = cpu_ppc_init("405");
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}
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if (!env) {
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fprintf(stderr, "Unable to initialize CPU!\n");
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exit(1);
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}
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ppc_dcr_init(env, NULL, NULL);
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/* interrupt controller */
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irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
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irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
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irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
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pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
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/* SDRAM controller */
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memset(ram_bases, 0, sizeof(ram_bases));
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memset(ram_sizes, 0, sizeof(ram_sizes));
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*ram_size = ppc4xx_sdram_adjust(*ram_size, PPC440EP_SDRAM_NR_BANKS,
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ram_bases, ram_sizes,
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ppc440ep_sdram_bank_sizes);
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/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
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ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_bases,
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ram_sizes, do_init);
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/* PCI */
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pci_irqs = qemu_malloc(sizeof(qemu_irq) * 4);
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pci_irqs[0] = pic[pci_irq_nrs[0]];
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pci_irqs[1] = pic[pci_irq_nrs[1]];
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pci_irqs[2] = pic[pci_irq_nrs[2]];
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pci_irqs[3] = pic[pci_irq_nrs[3]];
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*pcip = ppc4xx_pci_init(env, pci_irqs,
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PPC440EP_PCI_CONFIG,
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PPC440EP_PCI_INTACK,
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PPC440EP_PCI_SPECIAL,
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PPC440EP_PCI_REGS);
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if (!*pcip)
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printf("couldn't create PCI controller!\n");
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isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN);
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/* MMIO -- most "miscellaneous" devices live above 0xef600000. */
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mmio = ppc4xx_mmio_init(env, 0xef600000);
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if (serial_hds[0])
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ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
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if (serial_hds[1])
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ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
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return env;
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}
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