mirror of https://gitee.com/openkylin/qemu.git
395 lines
13 KiB
C
395 lines
13 KiB
C
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/*
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* FPU op helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "dyngen-exec.h"
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#include "helper.h"
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#define DT0 (env->dt0)
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#define DT1 (env->dt1)
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#define QT0 (env->qt0)
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#define QT1 (env->qt1)
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#define F_HELPER(name, p) void helper_f##name##p(void)
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#define F_BINOP(name) \
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float32 helper_f ## name ## s (float32 src1, float32 src2) \
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{ \
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return float32_ ## name (src1, src2, &env->fp_status); \
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} \
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F_HELPER(name, d) \
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{ \
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DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
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} \
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F_HELPER(name, q) \
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{ \
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QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
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}
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F_BINOP(add);
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F_BINOP(sub);
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F_BINOP(mul);
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F_BINOP(div);
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#undef F_BINOP
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void helper_fsmuld(float32 src1, float32 src2)
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{
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DT0 = float64_mul(float32_to_float64(src1, &env->fp_status),
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float32_to_float64(src2, &env->fp_status),
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&env->fp_status);
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}
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void helper_fdmulq(void)
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{
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QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
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float64_to_float128(DT1, &env->fp_status),
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&env->fp_status);
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}
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float32 helper_fnegs(float32 src)
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{
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return float32_chs(src);
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}
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#ifdef TARGET_SPARC64
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F_HELPER(neg, d)
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{
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DT0 = float64_chs(DT1);
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}
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F_HELPER(neg, q)
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{
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QT0 = float128_chs(QT1);
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}
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#endif
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/* Integer to float conversion. */
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float32 helper_fitos(int32_t src)
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{
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return int32_to_float32(src, &env->fp_status);
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}
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void helper_fitod(int32_t src)
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{
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DT0 = int32_to_float64(src, &env->fp_status);
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}
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void helper_fitoq(int32_t src)
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{
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QT0 = int32_to_float128(src, &env->fp_status);
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}
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#ifdef TARGET_SPARC64
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float32 helper_fxtos(void)
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{
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return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
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}
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F_HELPER(xto, d)
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{
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DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
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}
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F_HELPER(xto, q)
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{
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QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
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}
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#endif
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#undef F_HELPER
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/* floating point conversion */
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float32 helper_fdtos(void)
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{
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return float64_to_float32(DT1, &env->fp_status);
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}
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void helper_fstod(float32 src)
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{
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DT0 = float32_to_float64(src, &env->fp_status);
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}
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float32 helper_fqtos(void)
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{
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return float128_to_float32(QT1, &env->fp_status);
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}
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void helper_fstoq(float32 src)
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{
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QT0 = float32_to_float128(src, &env->fp_status);
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}
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void helper_fqtod(void)
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{
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DT0 = float128_to_float64(QT1, &env->fp_status);
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}
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void helper_fdtoq(void)
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{
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QT0 = float64_to_float128(DT1, &env->fp_status);
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}
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/* Float to integer conversion. */
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int32_t helper_fstoi(float32 src)
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{
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return float32_to_int32_round_to_zero(src, &env->fp_status);
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}
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int32_t helper_fdtoi(void)
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{
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return float64_to_int32_round_to_zero(DT1, &env->fp_status);
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}
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int32_t helper_fqtoi(void)
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{
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return float128_to_int32_round_to_zero(QT1, &env->fp_status);
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}
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#ifdef TARGET_SPARC64
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void helper_fstox(float32 src)
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{
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*((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status);
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}
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void helper_fdtox(void)
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{
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*((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
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}
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void helper_fqtox(void)
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{
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*((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
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}
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#endif
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float32 helper_fabss(float32 src)
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{
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return float32_abs(src);
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}
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#ifdef TARGET_SPARC64
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void helper_fabsd(void)
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{
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DT0 = float64_abs(DT1);
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}
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void helper_fabsq(void)
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{
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QT0 = float128_abs(QT1);
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}
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#endif
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float32 helper_fsqrts(float32 src)
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{
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return float32_sqrt(src, &env->fp_status);
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}
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void helper_fsqrtd(void)
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{
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DT0 = float64_sqrt(DT1, &env->fp_status);
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}
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void helper_fsqrtq(void)
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{
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QT0 = float128_sqrt(QT1, &env->fp_status);
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}
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#define GEN_FCMP(name, size, reg1, reg2, FS, E) \
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void glue(helper_, name) (void) \
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{ \
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env->fsr &= FSR_FTT_NMASK; \
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if (E && (glue(size, _is_any_nan)(reg1) || \
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glue(size, _is_any_nan)(reg2)) && \
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(env->fsr & FSR_NVM)) { \
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env->fsr |= FSR_NVC; \
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env->fsr |= FSR_FTT_IEEE_EXCP; \
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helper_raise_exception(env, TT_FP_EXCP); \
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} \
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switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
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case float_relation_unordered: \
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if ((env->fsr & FSR_NVM)) { \
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env->fsr |= FSR_NVC; \
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env->fsr |= FSR_FTT_IEEE_EXCP; \
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helper_raise_exception(env, TT_FP_EXCP); \
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} else { \
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
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env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
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env->fsr |= FSR_NVA; \
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} \
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break; \
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case float_relation_less: \
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
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env->fsr |= FSR_FCC0 << FS; \
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break; \
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case float_relation_greater: \
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
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env->fsr |= FSR_FCC1 << FS; \
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break; \
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default: \
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
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break; \
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} \
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}
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#define GEN_FCMPS(name, size, FS, E) \
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void glue(helper_, name)(float32 src1, float32 src2) \
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{ \
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env->fsr &= FSR_FTT_NMASK; \
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if (E && (glue(size, _is_any_nan)(src1) || \
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glue(size, _is_any_nan)(src2)) && \
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(env->fsr & FSR_NVM)) { \
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env->fsr |= FSR_NVC; \
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env->fsr |= FSR_FTT_IEEE_EXCP; \
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helper_raise_exception(env, TT_FP_EXCP); \
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} \
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switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
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case float_relation_unordered: \
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if ((env->fsr & FSR_NVM)) { \
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env->fsr |= FSR_NVC; \
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env->fsr |= FSR_FTT_IEEE_EXCP; \
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helper_raise_exception(env, TT_FP_EXCP); \
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} else { \
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
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env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
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env->fsr |= FSR_NVA; \
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} \
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break; \
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case float_relation_less: \
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
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env->fsr |= FSR_FCC0 << FS; \
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break; \
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case float_relation_greater: \
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
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env->fsr |= FSR_FCC1 << FS; \
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break; \
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default: \
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
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break; \
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} \
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}
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GEN_FCMPS(fcmps, float32, 0, 0);
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GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
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GEN_FCMPS(fcmpes, float32, 0, 1);
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GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
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GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
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GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
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#ifdef TARGET_SPARC64
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GEN_FCMPS(fcmps_fcc1, float32, 22, 0);
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GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
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GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
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GEN_FCMPS(fcmps_fcc2, float32, 24, 0);
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GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
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GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
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GEN_FCMPS(fcmps_fcc3, float32, 26, 0);
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GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
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GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
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GEN_FCMPS(fcmpes_fcc1, float32, 22, 1);
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GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
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GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
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GEN_FCMPS(fcmpes_fcc2, float32, 24, 1);
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GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
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GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
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GEN_FCMPS(fcmpes_fcc3, float32, 26, 1);
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GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
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GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
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#endif
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#undef GEN_FCMPS
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void helper_check_ieee_exceptions(void)
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{
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target_ulong status;
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status = get_float_exception_flags(&env->fp_status);
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if (status) {
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/* Copy IEEE 754 flags into FSR */
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if (status & float_flag_invalid) {
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env->fsr |= FSR_NVC;
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}
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if (status & float_flag_overflow) {
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env->fsr |= FSR_OFC;
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}
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if (status & float_flag_underflow) {
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env->fsr |= FSR_UFC;
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}
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if (status & float_flag_divbyzero) {
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env->fsr |= FSR_DZC;
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}
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if (status & float_flag_inexact) {
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env->fsr |= FSR_NXC;
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}
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if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
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/* Unmasked exception, generate a trap */
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env->fsr |= FSR_FTT_IEEE_EXCP;
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helper_raise_exception(env, TT_FP_EXCP);
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} else {
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/* Accumulate exceptions */
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env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
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}
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}
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}
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void helper_clear_float_exceptions(void)
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||
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{
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||
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|
set_float_exception_flags(0, &env->fp_status);
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||
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}
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|
|
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||
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static inline void set_fsr(void)
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||
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|
{
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||
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|
int rnd_mode;
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||
|
|
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||
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|
switch (env->fsr & FSR_RD_MASK) {
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||
|
|
case FSR_RD_NEAREST:
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||
|
|
rnd_mode = float_round_nearest_even;
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||
|
|
break;
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||
|
|
default:
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||
|
|
case FSR_RD_ZERO:
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||
|
|
rnd_mode = float_round_to_zero;
|
||
|
|
break;
|
||
|
|
case FSR_RD_POS:
|
||
|
|
rnd_mode = float_round_up;
|
||
|
|
break;
|
||
|
|
case FSR_RD_NEG:
|
||
|
|
rnd_mode = float_round_down;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
set_float_rounding_mode(rnd_mode, &env->fp_status);
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||
|
|
}
|
||
|
|
|
||
|
|
void helper_ldfsr(uint32_t new_fsr)
|
||
|
|
{
|
||
|
|
env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
|
||
|
|
set_fsr();
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef TARGET_SPARC64
|
||
|
|
void helper_ldxfsr(uint64_t new_fsr)
|
||
|
|
{
|
||
|
|
env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
|
||
|
|
set_fsr();
|
||
|
|
}
|
||
|
|
#endif
|