2012-07-20 15:50:48 +08:00
|
|
|
/*
|
|
|
|
* OpenRISC simulator for use as an IIS.
|
|
|
|
*
|
|
|
|
* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
|
|
|
|
* Feng Gao <gf91597@gmail.com>
|
|
|
|
*
|
|
|
|
* This library is free software; you can redistribute it and/or
|
|
|
|
* modify it under the terms of the GNU Lesser General Public
|
|
|
|
* License as published by the Free Software Foundation; either
|
|
|
|
* version 2 of the License, or (at your option) any later version.
|
|
|
|
*
|
|
|
|
* This library is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
|
|
* Lesser General Public License for more details.
|
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU Lesser General Public
|
|
|
|
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
|
|
|
*/
|
|
|
|
|
2013-02-04 22:40:22 +08:00
|
|
|
#include "hw/hw.h"
|
|
|
|
#include "hw/boards.h"
|
2012-07-20 15:50:48 +08:00
|
|
|
#include "elf.h"
|
2013-02-06 00:06:20 +08:00
|
|
|
#include "hw/char/serial.h"
|
2012-10-24 14:43:34 +08:00
|
|
|
#include "net/net.h"
|
2013-02-04 22:40:22 +08:00
|
|
|
#include "hw/loader.h"
|
2012-12-18 01:19:49 +08:00
|
|
|
#include "exec/address-spaces.h"
|
2012-12-18 01:20:04 +08:00
|
|
|
#include "sysemu/sysemu.h"
|
2013-02-04 22:40:22 +08:00
|
|
|
#include "hw/sysbus.h"
|
2012-12-18 01:20:04 +08:00
|
|
|
#include "sysemu/qtest.h"
|
2012-07-20 15:50:48 +08:00
|
|
|
|
|
|
|
#define KERNEL_LOAD_ADDR 0x100
|
|
|
|
|
|
|
|
static void main_cpu_reset(void *opaque)
|
|
|
|
{
|
|
|
|
OpenRISCCPU *cpu = opaque;
|
|
|
|
|
|
|
|
cpu_reset(CPU(cpu));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void openrisc_sim_net_init(MemoryRegion *address_space,
|
2012-10-23 18:30:10 +08:00
|
|
|
hwaddr base,
|
|
|
|
hwaddr descriptors,
|
2012-07-20 15:50:48 +08:00
|
|
|
qemu_irq irq, NICInfo *nd)
|
|
|
|
{
|
|
|
|
DeviceState *dev;
|
|
|
|
SysBusDevice *s;
|
|
|
|
|
|
|
|
dev = qdev_create(NULL, "open_eth");
|
|
|
|
qdev_set_nic_properties(dev, nd);
|
|
|
|
qdev_init_nofail(dev);
|
|
|
|
|
2013-01-20 09:47:33 +08:00
|
|
|
s = SYS_BUS_DEVICE(dev);
|
2012-07-20 15:50:48 +08:00
|
|
|
sysbus_connect_irq(s, 0, irq);
|
|
|
|
memory_region_add_subregion(address_space, base,
|
|
|
|
sysbus_mmio_get_region(s, 0));
|
|
|
|
memory_region_add_subregion(address_space, descriptors,
|
|
|
|
sysbus_mmio_get_region(s, 1));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cpu_openrisc_load_kernel(ram_addr_t ram_size,
|
|
|
|
const char *kernel_filename,
|
|
|
|
OpenRISCCPU *cpu)
|
|
|
|
{
|
|
|
|
long kernel_size;
|
|
|
|
uint64_t elf_entry;
|
2012-10-23 18:30:10 +08:00
|
|
|
hwaddr entry;
|
2012-07-20 15:50:48 +08:00
|
|
|
|
|
|
|
if (kernel_filename && !qtest_enabled()) {
|
|
|
|
kernel_size = load_elf(kernel_filename, NULL, NULL,
|
2015-05-11 14:29:10 +08:00
|
|
|
&elf_entry, NULL, NULL, 1, EM_OPENRISC, 1);
|
2012-07-20 15:50:48 +08:00
|
|
|
entry = elf_entry;
|
|
|
|
if (kernel_size < 0) {
|
|
|
|
kernel_size = load_uimage(kernel_filename,
|
2014-10-19 11:42:22 +08:00
|
|
|
&entry, NULL, NULL, NULL, NULL);
|
2012-07-20 15:50:48 +08:00
|
|
|
}
|
|
|
|
if (kernel_size < 0) {
|
|
|
|
kernel_size = load_image_targphys(kernel_filename,
|
|
|
|
KERNEL_LOAD_ADDR,
|
|
|
|
ram_size - KERNEL_LOAD_ADDR);
|
|
|
|
entry = KERNEL_LOAD_ADDR;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (kernel_size < 0) {
|
2013-07-23 18:31:24 +08:00
|
|
|
fprintf(stderr, "QEMU: couldn't load the kernel '%s'\n",
|
2012-07-20 15:50:48 +08:00
|
|
|
kernel_filename);
|
|
|
|
exit(1);
|
|
|
|
}
|
2013-08-21 08:54:29 +08:00
|
|
|
cpu->env.pc = entry;
|
2012-07-20 15:50:48 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-05-07 22:42:57 +08:00
|
|
|
static void openrisc_sim_init(MachineState *machine)
|
2012-07-20 15:50:48 +08:00
|
|
|
{
|
2014-05-07 22:42:57 +08:00
|
|
|
ram_addr_t ram_size = machine->ram_size;
|
|
|
|
const char *cpu_model = machine->cpu_model;
|
|
|
|
const char *kernel_filename = machine->kernel_filename;
|
2013-07-23 18:30:09 +08:00
|
|
|
OpenRISCCPU *cpu = NULL;
|
2012-07-20 15:50:48 +08:00
|
|
|
MemoryRegion *ram;
|
|
|
|
int n;
|
|
|
|
|
|
|
|
if (!cpu_model) {
|
|
|
|
cpu_model = "or1200";
|
|
|
|
}
|
|
|
|
|
|
|
|
for (n = 0; n < smp_cpus; n++) {
|
|
|
|
cpu = cpu_openrisc_init(cpu_model);
|
|
|
|
if (cpu == NULL) {
|
2013-07-23 18:31:24 +08:00
|
|
|
fprintf(stderr, "Unable to find CPU definition!\n");
|
2012-07-20 15:50:48 +08:00
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
qemu_register_reset(main_cpu_reset, cpu);
|
|
|
|
main_cpu_reset(cpu);
|
|
|
|
}
|
|
|
|
|
|
|
|
ram = g_malloc(sizeof(*ram));
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 22:51:43 +08:00
|
|
|
memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal);
|
2012-07-20 15:50:48 +08:00
|
|
|
vmstate_register_ram_global(ram);
|
|
|
|
memory_region_add_subregion(get_system_memory(), 0, ram);
|
|
|
|
|
|
|
|
cpu_openrisc_pic_init(cpu);
|
|
|
|
cpu_openrisc_clock_init(cpu);
|
|
|
|
|
|
|
|
serial_mm_init(get_system_memory(), 0x90000000, 0, cpu->env.irq[2],
|
|
|
|
115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
|
|
|
|
|
2012-07-24 23:35:11 +08:00
|
|
|
if (nd_table[0].used) {
|
2012-07-20 15:50:48 +08:00
|
|
|
openrisc_sim_net_init(get_system_memory(), 0x92000000,
|
|
|
|
0x92000400, cpu->env.irq[4], nd_table);
|
|
|
|
}
|
|
|
|
|
|
|
|
cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
|
|
|
|
}
|
|
|
|
|
2015-09-05 02:37:08 +08:00
|
|
|
static void openrisc_sim_machine_init(MachineClass *mc)
|
2012-07-20 15:50:48 +08:00
|
|
|
{
|
2015-09-05 02:37:08 +08:00
|
|
|
mc->desc = "or32 simulation";
|
|
|
|
mc->init = openrisc_sim_init;
|
|
|
|
mc->max_cpus = 1;
|
|
|
|
mc->is_default = 1;
|
2012-07-20 15:50:48 +08:00
|
|
|
}
|
|
|
|
|
2015-09-05 02:37:08 +08:00
|
|
|
DEFINE_MACHINE("or32-sim", openrisc_sim_machine_init)
|