mirror of https://gitee.com/openkylin/qemu.git
104 lines
3.8 KiB
C
104 lines
3.8 KiB
C
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/*
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* QEMU Cirrus CLGD 54xx VGA Emulator, ISA bus support
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*
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* Copyright (c) 2004 Fabrice Bellard
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* Copyright (c) 2004 Makoto Suzuki (suzu)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef CIRRUS_VGA_INTERNAL_H
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#define CIRRUS_VGA_INTERNAL_H
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#include "vga_int.h"
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/* IDs */
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#define CIRRUS_ID_CLGD5422 (0x23 << 2)
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#define CIRRUS_ID_CLGD5426 (0x24 << 2)
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#define CIRRUS_ID_CLGD5424 (0x25 << 2)
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#define CIRRUS_ID_CLGD5428 (0x26 << 2)
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#define CIRRUS_ID_CLGD5430 (0x28 << 2)
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#define CIRRUS_ID_CLGD5434 (0x2A << 2)
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#define CIRRUS_ID_CLGD5436 (0x2B << 2)
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#define CIRRUS_ID_CLGD5446 (0x2E << 2)
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extern const VMStateDescription vmstate_cirrus_vga;
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struct CirrusVGAState;
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typedef void (*cirrus_bitblt_rop_t)(struct CirrusVGAState *s,
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uint32_t dstaddr, uint32_t srcaddr,
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int dstpitch, int srcpitch,
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int bltwidth, int bltheight);
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typedef struct CirrusVGAState {
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VGACommonState vga;
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MemoryRegion cirrus_vga_io;
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MemoryRegion cirrus_linear_io;
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MemoryRegion cirrus_linear_bitblt_io;
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MemoryRegion cirrus_mmio_io;
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MemoryRegion pci_bar;
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bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
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MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
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MemoryRegion low_mem; /* always mapped, overridden by: */
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MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
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uint32_t cirrus_addr_mask;
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uint32_t linear_mmio_mask;
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uint8_t cirrus_shadow_gr0;
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uint8_t cirrus_shadow_gr1;
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uint8_t cirrus_hidden_dac_lockindex;
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uint8_t cirrus_hidden_dac_data;
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uint32_t cirrus_bank_base[2];
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uint32_t cirrus_bank_limit[2];
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uint8_t cirrus_hidden_palette[48];
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bool enable_blitter;
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int cirrus_blt_pixelwidth;
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int cirrus_blt_width;
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int cirrus_blt_height;
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int cirrus_blt_dstpitch;
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int cirrus_blt_srcpitch;
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uint32_t cirrus_blt_fgcol;
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uint32_t cirrus_blt_bgcol;
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uint32_t cirrus_blt_dstaddr;
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uint32_t cirrus_blt_srcaddr;
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uint8_t cirrus_blt_mode;
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uint8_t cirrus_blt_modeext;
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cirrus_bitblt_rop_t cirrus_rop;
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#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
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uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
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uint8_t *cirrus_srcptr;
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uint8_t *cirrus_srcptr_end;
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uint32_t cirrus_srccounter;
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/* hwcursor display state */
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int last_hw_cursor_size;
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int last_hw_cursor_x;
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int last_hw_cursor_y;
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int last_hw_cursor_y_start;
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int last_hw_cursor_y_end;
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int real_vram_size; /* XXX: suppress that */
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int device_id;
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int bustype;
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} CirrusVGAState;
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void cirrus_init_common(CirrusVGAState *s, Object *owner,
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int device_id, int is_pci,
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MemoryRegion *system_memory, MemoryRegion *system_io);
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#endif
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