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qemu/default-configs/mips-softmmu-common.mak

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default-configs: add mips-softmmu-common.mak Add mips-softmmu-common.mak and include it in existing mips*-softmmu.mak files to avoid having to repeat CONFIG defines four times. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-02 21:21:11 +08:00
# Common mips*-softmmu CONFIG defines
include pci.mak
include sound.mak
include usb.mak
CONFIG_ESP=y
CONFIG_VGA_ISA=y
CONFIG_VGA_ISA_MM=y
CONFIG_VGA_CIRRUS=y
CONFIG_VMWARE_VGA=y
CONFIG_SERIAL=y
Split serial-isa into its own config option At present, the core device model code for 8250-like serial ports (serial.c) and the code for serial ports attached to ISA-style legacy IO (serial-isa.c) are both controlled by the CONFIG_SERIAL variable. There are lots and lots of embedded platforms that have 8250-like serial ports but have never had anything resembling ISA legacy IO. Therefore, split serial-isa into its own CONFIG_SERIAL_ISA option so it can be disabled for platforms where it's not appropriate. For now, I enabled CONFIG_SERIAL_ISA in every default-config where CONFIG_SERIAL is enabled, excepting microblaze, or32, and xtensa. As best as I can tell, those platforms never used legacy ISA, and also don't include PCI support (which would allow connection of a PCI->ISA bridge and/or a southbridge including legacy ISA serial ports). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
2016-02-08 08:36:54 +08:00
CONFIG_SERIAL_ISA=y
default-configs: add mips-softmmu-common.mak Add mips-softmmu-common.mak and include it in existing mips*-softmmu.mak files to avoid having to repeat CONFIG defines four times. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-02 21:21:11 +08:00
CONFIG_PARALLEL=y
CONFIG_I8254=y
CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
CONFIG_ACPI_X86=y
CONFIG_ACPI_MEMORY_HOTPLUG=y
pc: memhp: move nvdimm hotplug out of memory hotplug as they use completely different way to handle hotplug event Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2016-11-07 19:13:38 +08:00
CONFIG_ACPI_NVDIMM=y
default-configs: add mips-softmmu-common.mak Add mips-softmmu-common.mak and include it in existing mips*-softmmu.mak files to avoid having to repeat CONFIG defines four times. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-02 21:21:11 +08:00
CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_PIIX4=y
CONFIG_IDE_ISA=y
CONFIG_IDE_PIIX=y
CONFIG_NE2000_ISA=y
CONFIG_MIPSNET=y
CONFIG_PFLASH_CFI01=y
CONFIG_I8259=y
CONFIG_MC146818RTC=y
CONFIG_ISA_TESTDEV=y
CONFIG_EMPTY_SLOT=y
hw/mips: implement generic MIPS Coherent Processing System container Implement generic MIPS Coherent Processing System (CPS) which in this commit just creates VPs, but it will serve as a container also for other components like Global Configuration Registers and Cluster Power Controller. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-15 17:59:26 +08:00
CONFIG_MIPS_CPS=y
hw/mips: implement ITC Configuration Tags and Storage Cells Implement ITC as a single object consisting of two memory regions: 1) tag_io: ITC Configuration Tags (i.e. ITCAddressMap{0,1} registers) which are accessible by the CPU via CACHE instruction. Also adding MemoryRegion *itc_tag to the CPUMIPSState so that CACHE instruction will dispatch reads/writes directly. 2) storage_io: memory-mapped ITC Storage whose address space is configurable (i.e. enabled/remapped/resized) by writing to ITCAddressMap{0,1} registers. ITC Storage contains FIFO and Semaphore cells. Read-only FIFO bit in the ITC cell tag indicates the type of the cell. If the ITC Storage contains both types of cells then FIFOs are located before Semaphores. Since issuing thread can get blocked on the access to a cell (in E/F Synchronized and P/V Synchronized Views) each cell has a bitmap to track which threads are currently blocked. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-25 21:49:30 +08:00
CONFIG_MIPS_ITU=y