2011-09-06 07:55:25 +08:00
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/*
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2016-06-29 17:05:55 +08:00
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#ifndef XTENSA_CPU_H
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#define XTENSA_CPU_H
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2011-09-06 07:55:25 +08:00
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2014-03-29 00:48:12 +08:00
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#define ALIGNED_ONLY
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2011-09-06 07:55:25 +08:00
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#define TARGET_LONG_BITS 32
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2012-03-14 08:38:32 +08:00
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#define CPUArchState struct CPUXtensaState
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2011-09-06 07:55:25 +08:00
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#include "qemu-common.h"
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2016-03-15 20:49:25 +08:00
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#include "cpu-qom.h"
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2012-12-18 01:19:49 +08:00
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#include "exec/cpu-defs.h"
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2012-09-19 08:23:54 +08:00
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#include "fpu/softfloat.h"
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2011-09-06 07:55:25 +08:00
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#define NB_MMU_MODES 4
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#define TARGET_PHYS_ADDR_SPACE_BITS 32
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#define TARGET_VIRT_ADDR_SPACE_BITS 32
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#define TARGET_PAGE_BITS 12
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2011-09-06 07:55:27 +08:00
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enum {
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/* Additional instructions */
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XTENSA_OPTION_CODE_DENSITY,
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XTENSA_OPTION_LOOP,
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XTENSA_OPTION_EXTENDED_L32R,
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XTENSA_OPTION_16_BIT_IMUL,
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XTENSA_OPTION_32_BIT_IMUL,
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2011-10-16 06:56:01 +08:00
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XTENSA_OPTION_32_BIT_IMUL_HIGH,
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2011-09-06 07:55:27 +08:00
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XTENSA_OPTION_32_BIT_IDIV,
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XTENSA_OPTION_MAC16,
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2011-10-16 06:56:01 +08:00
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XTENSA_OPTION_MISC_OP_NSA,
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XTENSA_OPTION_MISC_OP_MINMAX,
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XTENSA_OPTION_MISC_OP_SEXT,
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XTENSA_OPTION_MISC_OP_CLAMPS,
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2011-09-06 07:55:27 +08:00
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XTENSA_OPTION_COPROCESSOR,
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XTENSA_OPTION_BOOLEAN,
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XTENSA_OPTION_FP_COPROCESSOR,
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XTENSA_OPTION_MP_SYNCHRO,
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XTENSA_OPTION_CONDITIONAL_STORE,
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2012-12-05 11:15:20 +08:00
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XTENSA_OPTION_ATOMCTL,
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2015-07-12 07:10:17 +08:00
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XTENSA_OPTION_DEPBITS,
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2011-09-06 07:55:27 +08:00
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/* Interrupts and exceptions */
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XTENSA_OPTION_EXCEPTION,
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XTENSA_OPTION_RELOCATABLE_VECTOR,
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XTENSA_OPTION_UNALIGNED_EXCEPTION,
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XTENSA_OPTION_INTERRUPT,
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XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
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XTENSA_OPTION_TIMER_INTERRUPT,
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/* Local memory */
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XTENSA_OPTION_ICACHE,
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XTENSA_OPTION_ICACHE_TEST,
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XTENSA_OPTION_ICACHE_INDEX_LOCK,
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XTENSA_OPTION_DCACHE,
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XTENSA_OPTION_DCACHE_TEST,
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XTENSA_OPTION_DCACHE_INDEX_LOCK,
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XTENSA_OPTION_IRAM,
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XTENSA_OPTION_IROM,
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XTENSA_OPTION_DRAM,
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XTENSA_OPTION_DROM,
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XTENSA_OPTION_XLMI,
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XTENSA_OPTION_HW_ALIGNMENT,
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XTENSA_OPTION_MEMORY_ECC_PARITY,
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/* Memory protection and translation */
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XTENSA_OPTION_REGION_PROTECTION,
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XTENSA_OPTION_REGION_TRANSLATION,
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XTENSA_OPTION_MMU,
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2012-12-05 11:15:21 +08:00
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XTENSA_OPTION_CACHEATTR,
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2011-09-06 07:55:27 +08:00
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/* Other */
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XTENSA_OPTION_WINDOWED_REGISTER,
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XTENSA_OPTION_PROCESSOR_INTERFACE,
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XTENSA_OPTION_MISC_SR,
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XTENSA_OPTION_THREAD_POINTER,
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XTENSA_OPTION_PROCESSOR_ID,
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XTENSA_OPTION_DEBUG,
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XTENSA_OPTION_TRACE_PORT,
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};
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2011-09-06 07:55:33 +08:00
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enum {
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THREADPTR = 231,
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FCR = 232,
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FSR = 233,
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};
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2011-09-06 07:55:35 +08:00
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enum {
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2011-09-06 07:55:44 +08:00
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LBEG = 0,
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LEND = 1,
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LCOUNT = 2,
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2011-09-06 07:55:35 +08:00
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SAR = 3,
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2011-09-06 07:55:54 +08:00
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BR = 4,
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2011-09-06 07:55:45 +08:00
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LITBASE = 5,
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2011-09-06 07:55:36 +08:00
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SCOMPARE1 = 12,
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2011-10-10 10:25:40 +08:00
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ACCLO = 16,
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ACCHI = 17,
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MR = 32,
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2011-09-06 07:55:43 +08:00
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WINDOW_BASE = 72,
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WINDOW_START = 73,
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2011-09-06 07:55:53 +08:00
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PTEVADDR = 83,
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RASID = 90,
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ITLBCFG = 91,
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DTLBCFG = 92,
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2012-01-13 13:21:32 +08:00
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IBREAKENABLE = 96,
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2012-12-05 11:15:21 +08:00
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CACHEATTR = 98,
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2012-12-05 11:15:20 +08:00
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ATOMCTL = 99,
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2012-01-13 13:21:32 +08:00
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IBREAKA = 128,
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2012-01-29 09:28:21 +08:00
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DBREAKA = 144,
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DBREAKC = 160,
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2014-02-16 00:49:09 +08:00
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CONFIGID0 = 176,
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2011-09-06 07:55:41 +08:00
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EPC1 = 177,
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DEPC = 192,
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2011-09-06 07:55:48 +08:00
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EPS2 = 194,
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2014-02-16 00:49:09 +08:00
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CONFIGID1 = 208,
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2011-09-06 07:55:41 +08:00
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EXCSAVE1 = 209,
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2011-09-06 07:55:50 +08:00
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CPENABLE = 224,
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2011-09-06 07:55:48 +08:00
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INTSET = 226,
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INTCLEAR = 227,
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INTENABLE = 228,
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2011-09-06 07:55:40 +08:00
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PS = 230,
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2011-09-06 07:55:51 +08:00
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VECBASE = 231,
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2011-09-06 07:55:41 +08:00
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EXCCAUSE = 232,
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2011-12-14 06:13:40 +08:00
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DEBUGCAUSE = 233,
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2011-09-06 07:55:48 +08:00
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CCOUNT = 234,
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2011-09-06 07:55:50 +08:00
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PRID = 235,
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2012-01-15 09:40:50 +08:00
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ICOUNT = 236,
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ICOUNTLEVEL = 237,
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2011-09-06 07:55:41 +08:00
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EXCVADDR = 238,
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2011-09-06 07:55:48 +08:00
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CCOMPARE = 240,
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2012-12-05 11:15:24 +08:00
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MISC = 244,
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2011-09-06 07:55:35 +08:00
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};
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2011-09-06 07:55:40 +08:00
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#define PS_INTLEVEL 0xf
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#define PS_INTLEVEL_SHIFT 0
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#define PS_EXCM 0x10
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#define PS_UM 0x20
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#define PS_RING 0xc0
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#define PS_RING_SHIFT 6
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#define PS_OWB 0xf00
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#define PS_OWB_SHIFT 8
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#define PS_CALLINC 0x30000
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#define PS_CALLINC_SHIFT 16
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#define PS_CALLINC_LEN 2
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#define PS_WOE 0x40000
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2011-12-14 06:13:40 +08:00
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#define DEBUGCAUSE_IC 0x1
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#define DEBUGCAUSE_IB 0x2
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#define DEBUGCAUSE_DB 0x4
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#define DEBUGCAUSE_BI 0x8
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#define DEBUGCAUSE_BN 0x10
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#define DEBUGCAUSE_DI 0x20
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#define DEBUGCAUSE_DBNUM 0xf00
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#define DEBUGCAUSE_DBNUM_SHIFT 8
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2012-01-29 09:28:21 +08:00
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#define DBREAKC_SB 0x80000000
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#define DBREAKC_LB 0x40000000
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#define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
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#define DBREAKC_MASK 0x3f
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2011-09-06 07:55:43 +08:00
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#define MAX_NAREG 64
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2011-09-06 07:55:48 +08:00
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#define MAX_NINTERRUPT 32
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#define MAX_NLEVEL 6
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#define MAX_NNMI 1
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#define MAX_NCCOMPARE 3
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2011-09-06 07:55:53 +08:00
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#define MAX_TLB_WAY_SIZE 8
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2012-01-29 09:28:21 +08:00
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#define MAX_NDBREAK 2
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2011-09-06 07:55:53 +08:00
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#define REGION_PAGE_MASK 0xe0000000
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2011-09-06 07:55:43 +08:00
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2012-12-05 11:15:20 +08:00
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#define PAGE_CACHE_MASK 0x700
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#define PAGE_CACHE_SHIFT 8
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#define PAGE_CACHE_INVALID 0x000
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#define PAGE_CACHE_BYPASS 0x100
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#define PAGE_CACHE_WT 0x200
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#define PAGE_CACHE_WB 0x400
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#define PAGE_CACHE_ISOLATE 0x600
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2011-09-06 07:55:41 +08:00
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enum {
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/* Static vectors */
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EXC_RESET,
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EXC_MEMORY_ERROR,
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/* Dynamic vectors */
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EXC_WINDOW_OVERFLOW4,
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EXC_WINDOW_UNDERFLOW4,
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EXC_WINDOW_OVERFLOW8,
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EXC_WINDOW_UNDERFLOW8,
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EXC_WINDOW_OVERFLOW12,
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EXC_WINDOW_UNDERFLOW12,
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EXC_IRQ,
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EXC_KERNEL,
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EXC_USER,
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EXC_DOUBLE,
|
2012-01-13 13:21:32 +08:00
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EXC_DEBUG,
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2011-09-06 07:55:41 +08:00
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EXC_MAX
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};
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enum {
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ILLEGAL_INSTRUCTION_CAUSE = 0,
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SYSCALL_CAUSE,
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INSTRUCTION_FETCH_ERROR_CAUSE,
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LOAD_STORE_ERROR_CAUSE,
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LEVEL1_INTERRUPT_CAUSE,
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ALLOCA_CAUSE,
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INTEGER_DIVIDE_BY_ZERO_CAUSE,
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PRIVILEGED_CAUSE = 8,
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LOAD_STORE_ALIGNMENT_CAUSE,
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INSTR_PIF_DATA_ERROR_CAUSE = 12,
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LOAD_STORE_PIF_DATA_ERROR_CAUSE,
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INSTR_PIF_ADDR_ERROR_CAUSE,
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LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
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INST_TLB_MISS_CAUSE,
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INST_TLB_MULTI_HIT_CAUSE,
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INST_FETCH_PRIVILEGE_CAUSE,
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INST_FETCH_PROHIBITED_CAUSE = 20,
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LOAD_STORE_TLB_MISS_CAUSE = 24,
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LOAD_STORE_TLB_MULTI_HIT_CAUSE,
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LOAD_STORE_PRIVILEGE_CAUSE,
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LOAD_PROHIBITED_CAUSE = 28,
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STORE_PROHIBITED_CAUSE,
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COPROCESSOR0_DISABLED = 32,
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};
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2011-09-06 07:55:48 +08:00
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typedef enum {
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INTTYPE_LEVEL,
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INTTYPE_EDGE,
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INTTYPE_NMI,
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INTTYPE_SOFTWARE,
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INTTYPE_TIMER,
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INTTYPE_DEBUG,
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INTTYPE_WRITE_ERR,
|
2014-02-15 23:16:33 +08:00
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INTTYPE_PROFILING,
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2011-09-06 07:55:48 +08:00
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INTTYPE_MAX
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} interrupt_type;
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2011-09-06 07:55:53 +08:00
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typedef struct xtensa_tlb_entry {
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uint32_t vaddr;
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uint32_t paddr;
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uint8_t asid;
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uint8_t attr;
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bool variable;
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} xtensa_tlb_entry;
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typedef struct xtensa_tlb {
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unsigned nways;
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const unsigned way_size[10];
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bool varway56;
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unsigned nrefillentries;
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} xtensa_tlb;
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|
2011-09-06 07:55:52 +08:00
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typedef struct XtensaGdbReg {
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int targno;
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int type;
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int group;
|
2015-06-29 15:50:03 +08:00
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unsigned size;
|
2011-09-06 07:55:52 +08:00
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} XtensaGdbReg;
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typedef struct XtensaGdbRegmap {
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int num_regs;
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int num_core_regs;
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/* PC + a + ar + sr + ur */
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XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
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} XtensaGdbRegmap;
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|
|
2016-03-15 20:49:25 +08:00
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|
|
struct XtensaConfig {
|
2011-09-06 07:55:27 +08:00
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const char *name;
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uint64_t options;
|
2011-09-06 07:55:52 +08:00
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XtensaGdbRegmap gdb_regmap;
|
2011-09-06 07:55:43 +08:00
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unsigned nareg;
|
2011-09-06 07:55:41 +08:00
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int excm_level;
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int ndepc;
|
2011-09-06 07:55:51 +08:00
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uint32_t vecbase;
|
2011-09-06 07:55:41 +08:00
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uint32_t exception_vector[EXC_MAX];
|
2011-09-06 07:55:48 +08:00
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unsigned ninterrupt;
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unsigned nlevel;
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uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
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uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
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|
|
uint32_t inttype_mask[INTTYPE_MAX];
|
|
|
|
struct {
|
|
|
|
uint32_t level;
|
|
|
|
interrupt_type inttype;
|
|
|
|
} interrupt[MAX_NINTERRUPT];
|
|
|
|
unsigned nccompare;
|
|
|
|
uint32_t timerint[MAX_NCCOMPARE];
|
2011-10-16 06:56:03 +08:00
|
|
|
unsigned nextint;
|
|
|
|
unsigned extint[MAX_NINTERRUPT];
|
2011-12-14 06:13:40 +08:00
|
|
|
|
|
|
|
unsigned debug_level;
|
|
|
|
unsigned nibreak;
|
|
|
|
unsigned ndbreak;
|
|
|
|
|
2014-02-16 00:49:09 +08:00
|
|
|
uint32_t configid[2];
|
|
|
|
|
2011-09-06 07:55:48 +08:00
|
|
|
uint32_t clock_freq_khz;
|
2011-09-06 07:55:53 +08:00
|
|
|
|
|
|
|
xtensa_tlb itlb;
|
|
|
|
xtensa_tlb dtlb;
|
2016-03-15 20:49:25 +08:00
|
|
|
};
|
2011-09-06 07:55:27 +08:00
|
|
|
|
2011-10-16 06:56:04 +08:00
|
|
|
typedef struct XtensaConfigList {
|
|
|
|
const XtensaConfig *config;
|
|
|
|
struct XtensaConfigList *next;
|
|
|
|
} XtensaConfigList;
|
|
|
|
|
2015-06-29 15:50:03 +08:00
|
|
|
#ifdef HOST_WORDS_BIGENDIAN
|
|
|
|
enum {
|
|
|
|
FP_F32_HIGH,
|
|
|
|
FP_F32_LOW,
|
|
|
|
};
|
|
|
|
#else
|
|
|
|
enum {
|
|
|
|
FP_F32_LOW,
|
|
|
|
FP_F32_HIGH,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2011-09-06 07:55:25 +08:00
|
|
|
typedef struct CPUXtensaState {
|
2011-09-06 07:55:27 +08:00
|
|
|
const XtensaConfig *config;
|
2011-09-06 07:55:25 +08:00
|
|
|
uint32_t regs[16];
|
|
|
|
uint32_t pc;
|
|
|
|
uint32_t sregs[256];
|
2011-09-06 07:55:33 +08:00
|
|
|
uint32_t uregs[256];
|
2011-09-06 07:55:43 +08:00
|
|
|
uint32_t phys_regs[MAX_NAREG];
|
2015-06-29 15:50:03 +08:00
|
|
|
union {
|
|
|
|
float32 f32[2];
|
|
|
|
float64 f64;
|
|
|
|
} fregs[16];
|
2012-09-19 08:23:54 +08:00
|
|
|
float_status fp_status;
|
2011-09-06 07:55:25 +08:00
|
|
|
|
2011-09-06 07:55:53 +08:00
|
|
|
xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
|
|
|
|
xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
|
|
|
|
unsigned autorefill_idx;
|
|
|
|
|
2011-09-06 07:55:48 +08:00
|
|
|
int pending_irq_level; /* level of last raised IRQ */
|
|
|
|
void **irq_inputs;
|
|
|
|
QEMUTimer *ccompare_timer;
|
|
|
|
uint32_t wake_ccount;
|
|
|
|
int64_t halt_clock;
|
|
|
|
|
2011-09-06 07:55:41 +08:00
|
|
|
int exception_taken;
|
|
|
|
|
2012-01-29 09:28:21 +08:00
|
|
|
/* Watchpoints for DBREAK registers */
|
2013-08-27 00:23:18 +08:00
|
|
|
struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
|
2012-01-29 09:28:21 +08:00
|
|
|
|
2011-09-06 07:55:25 +08:00
|
|
|
CPU_COMMON
|
|
|
|
} CPUXtensaState;
|
|
|
|
|
2016-03-15 20:49:25 +08:00
|
|
|
/**
|
|
|
|
* XtensaCPU:
|
|
|
|
* @env: #CPUXtensaState
|
|
|
|
*
|
|
|
|
* An Xtensa CPU.
|
|
|
|
*/
|
|
|
|
struct XtensaCPU {
|
|
|
|
/*< private >*/
|
|
|
|
CPUState parent_obj;
|
|
|
|
/*< public >*/
|
|
|
|
|
|
|
|
CPUXtensaState env;
|
|
|
|
};
|
|
|
|
|
|
|
|
static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
|
|
|
|
{
|
|
|
|
return container_of(env, XtensaCPU, env);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
|
|
|
|
|
|
|
|
#define ENV_OFFSET offsetof(XtensaCPU, env)
|
|
|
|
|
|
|
|
void xtensa_cpu_do_interrupt(CPUState *cpu);
|
|
|
|
bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
|
|
|
|
void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr,
|
|
|
|
bool is_write, bool is_exec, int opaque,
|
|
|
|
unsigned size);
|
|
|
|
void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
|
|
|
|
fprintf_function cpu_fprintf, int flags);
|
|
|
|
hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
|
|
|
|
int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
|
|
|
|
int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
|
|
|
|
void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
|
2016-06-14 20:26:17 +08:00
|
|
|
MMUAccessType access_type,
|
|
|
|
int mmu_idx, uintptr_t retaddr);
|
2012-05-06 18:41:53 +08:00
|
|
|
|
2011-09-06 07:55:25 +08:00
|
|
|
#define cpu_signal_handler cpu_xtensa_signal_handler
|
|
|
|
#define cpu_list xtensa_cpu_list
|
|
|
|
|
2012-08-08 18:07:14 +08:00
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
|
|
#define XTENSA_DEFAULT_CPU_MODEL "fsf"
|
|
|
|
#else
|
|
|
|
#define XTENSA_DEFAULT_CPU_MODEL "dc232b"
|
|
|
|
#endif
|
|
|
|
|
2012-05-06 18:41:53 +08:00
|
|
|
XtensaCPU *cpu_xtensa_init(const char *cpu_model);
|
|
|
|
|
2015-02-27 04:37:49 +08:00
|
|
|
#define cpu_init(cpu_model) CPU(cpu_xtensa_init(cpu_model))
|
2012-05-06 18:41:53 +08:00
|
|
|
|
2011-09-06 07:55:25 +08:00
|
|
|
void xtensa_translate_init(void);
|
2014-09-12 21:06:48 +08:00
|
|
|
void xtensa_breakpoint_handler(CPUState *cs);
|
2015-07-01 18:00:29 +08:00
|
|
|
void xtensa_finalize_config(XtensaConfig *config);
|
2011-10-16 06:56:04 +08:00
|
|
|
void xtensa_register_core(XtensaConfigList *node);
|
2011-09-06 07:55:48 +08:00
|
|
|
void check_interrupts(CPUXtensaState *s);
|
2012-03-14 08:38:23 +08:00
|
|
|
void xtensa_irq_init(CPUXtensaState *env);
|
|
|
|
void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
|
|
|
|
void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
|
|
|
|
void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
|
|
|
|
void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
|
2011-09-06 07:55:25 +08:00
|
|
|
int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
|
|
|
|
void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
|
2012-03-14 08:38:23 +08:00
|
|
|
void xtensa_sync_window_from_phys(CPUXtensaState *env);
|
|
|
|
void xtensa_sync_phys_from_window(CPUXtensaState *env);
|
|
|
|
uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
|
|
|
|
void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
|
2011-09-06 07:55:53 +08:00
|
|
|
uint32_t *vpn, uint32_t wi, uint32_t *ei);
|
2012-03-14 08:38:23 +08:00
|
|
|
int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
|
2011-09-06 07:55:53 +08:00
|
|
|
uint32_t *pwi, uint32_t *pei, uint8_t *pring);
|
2012-05-27 22:34:51 +08:00
|
|
|
void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
|
|
|
|
xtensa_tlb_entry *entry, bool dtlb,
|
|
|
|
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
|
2012-03-14 08:38:23 +08:00
|
|
|
void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
|
2011-09-06 07:55:53 +08:00
|
|
|
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
|
2012-05-27 22:34:52 +08:00
|
|
|
int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
|
2011-09-06 07:55:53 +08:00
|
|
|
uint32_t vaddr, int is_write, int mmu_idx,
|
|
|
|
uint32_t *paddr, uint32_t *page_size, unsigned *access);
|
2012-04-12 00:24:49 +08:00
|
|
|
void reset_mmu(CPUXtensaState *env);
|
2012-03-14 08:38:23 +08:00
|
|
|
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
|
|
|
|
void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
|
2011-09-06 07:55:53 +08:00
|
|
|
|
2011-09-06 07:55:25 +08:00
|
|
|
|
2011-09-06 07:55:27 +08:00
|
|
|
#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
|
2012-12-05 11:15:22 +08:00
|
|
|
#define XTENSA_OPTION_ALL (~(uint64_t)0)
|
2011-09-06 07:55:27 +08:00
|
|
|
|
2011-09-06 07:55:53 +08:00
|
|
|
static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
|
|
|
|
uint64_t opt)
|
|
|
|
{
|
|
|
|
return (config->options & opt) != 0;
|
|
|
|
}
|
|
|
|
|
2011-09-06 07:55:27 +08:00
|
|
|
static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
|
|
|
|
{
|
2011-09-06 07:55:53 +08:00
|
|
|
return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
|
2011-09-06 07:55:27 +08:00
|
|
|
}
|
|
|
|
|
2012-03-14 08:38:23 +08:00
|
|
|
static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
|
2011-09-06 07:55:41 +08:00
|
|
|
{
|
|
|
|
int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
|
|
|
|
if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
|
|
|
|
level = env->config->excm_level;
|
|
|
|
}
|
|
|
|
return level;
|
|
|
|
}
|
|
|
|
|
2012-03-14 08:38:23 +08:00
|
|
|
static inline int xtensa_get_ring(const CPUXtensaState *env)
|
2011-09-06 07:55:40 +08:00
|
|
|
{
|
|
|
|
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
|
|
|
|
return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-03-14 08:38:23 +08:00
|
|
|
static inline int xtensa_get_cring(const CPUXtensaState *env)
|
2011-09-06 07:55:40 +08:00
|
|
|
{
|
|
|
|
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
|
|
|
|
(env->sregs[PS] & PS_EXCM) == 0) {
|
|
|
|
return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-03-14 08:38:23 +08:00
|
|
|
static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
|
2011-09-06 07:55:53 +08:00
|
|
|
bool dtlb, unsigned wi, unsigned ei)
|
|
|
|
{
|
|
|
|
return dtlb ?
|
|
|
|
env->dtlb[wi] + ei :
|
|
|
|
env->itlb[wi] + ei;
|
|
|
|
}
|
|
|
|
|
2014-11-08 02:11:07 +08:00
|
|
|
static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
|
|
|
|
{
|
|
|
|
return env->sregs[WINDOW_START] |
|
|
|
|
(env->sregs[WINDOW_START] << env->config->nareg / 4);
|
|
|
|
}
|
|
|
|
|
2011-09-06 07:55:40 +08:00
|
|
|
/* MMU modes definitions */
|
|
|
|
#define MMU_MODE0_SUFFIX _ring0
|
|
|
|
#define MMU_MODE1_SUFFIX _ring1
|
|
|
|
#define MMU_MODE2_SUFFIX _ring2
|
|
|
|
#define MMU_MODE3_SUFFIX _ring3
|
|
|
|
|
2015-08-17 15:34:10 +08:00
|
|
|
static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
|
2011-09-06 07:55:25 +08:00
|
|
|
{
|
2011-09-06 07:55:40 +08:00
|
|
|
return xtensa_get_cring(env);
|
2011-09-06 07:55:25 +08:00
|
|
|
}
|
|
|
|
|
2011-09-06 07:55:40 +08:00
|
|
|
#define XTENSA_TBFLAG_RING_MASK 0x3
|
|
|
|
#define XTENSA_TBFLAG_EXCM 0x4
|
2011-09-06 07:55:45 +08:00
|
|
|
#define XTENSA_TBFLAG_LITBASE 0x8
|
2012-01-13 13:21:32 +08:00
|
|
|
#define XTENSA_TBFLAG_DEBUG 0x10
|
2012-01-15 09:40:50 +08:00
|
|
|
#define XTENSA_TBFLAG_ICOUNT 0x20
|
2012-09-19 08:23:59 +08:00
|
|
|
#define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
|
|
|
|
#define XTENSA_TBFLAG_CPENABLE_SHIFT 6
|
2013-03-04 11:02:00 +08:00
|
|
|
#define XTENSA_TBFLAG_EXCEPTION 0x4000
|
2014-10-30 23:07:47 +08:00
|
|
|
#define XTENSA_TBFLAG_WINDOW_MASK 0x18000
|
|
|
|
#define XTENSA_TBFLAG_WINDOW_SHIFT 15
|
2011-09-06 07:55:40 +08:00
|
|
|
|
2012-03-14 08:38:23 +08:00
|
|
|
static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
|
2016-04-08 01:19:22 +08:00
|
|
|
target_ulong *cs_base, uint32_t *flags)
|
2011-09-06 07:55:25 +08:00
|
|
|
{
|
2014-03-10 03:02:29 +08:00
|
|
|
CPUState *cs = CPU(xtensa_env_get_cpu(env));
|
|
|
|
|
2011-09-06 07:55:25 +08:00
|
|
|
*pc = env->pc;
|
|
|
|
*cs_base = 0;
|
|
|
|
*flags = 0;
|
2011-09-06 07:55:40 +08:00
|
|
|
*flags |= xtensa_get_ring(env);
|
|
|
|
if (env->sregs[PS] & PS_EXCM) {
|
|
|
|
*flags |= XTENSA_TBFLAG_EXCM;
|
|
|
|
}
|
2011-09-06 07:55:45 +08:00
|
|
|
if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
|
|
|
|
(env->sregs[LITBASE] & 1)) {
|
|
|
|
*flags |= XTENSA_TBFLAG_LITBASE;
|
|
|
|
}
|
2012-01-13 13:21:32 +08:00
|
|
|
if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
|
|
|
|
if (xtensa_get_cintlevel(env) < env->config->debug_level) {
|
|
|
|
*flags |= XTENSA_TBFLAG_DEBUG;
|
|
|
|
}
|
2012-01-15 09:40:50 +08:00
|
|
|
if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
|
|
|
|
*flags |= XTENSA_TBFLAG_ICOUNT;
|
|
|
|
}
|
2012-01-13 13:21:32 +08:00
|
|
|
}
|
2012-09-19 08:23:59 +08:00
|
|
|
if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
|
|
|
|
*flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
|
|
|
|
}
|
2014-03-10 03:02:29 +08:00
|
|
|
if (cs->singlestep_enabled && env->exception_taken) {
|
2013-03-04 11:02:00 +08:00
|
|
|
*flags |= XTENSA_TBFLAG_EXCEPTION;
|
|
|
|
}
|
2014-10-30 23:07:47 +08:00
|
|
|
if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
|
|
|
|
(env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
|
|
|
|
uint32_t windowstart = xtensa_replicate_windowstart(env) >>
|
|
|
|
(env->sregs[WINDOW_BASE] + 1);
|
|
|
|
uint32_t w = ctz32(windowstart | 0x8);
|
|
|
|
|
|
|
|
*flags |= w << XTENSA_TBFLAG_WINDOW_SHIFT;
|
|
|
|
} else {
|
|
|
|
*flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
|
|
|
|
}
|
2011-09-06 07:55:25 +08:00
|
|
|
}
|
|
|
|
|
2012-12-18 01:19:49 +08:00
|
|
|
#include "exec/cpu-all.h"
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2011-09-06 07:55:25 +08:00
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#endif
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