2009-03-03 00:42:04 +08:00
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#if !defined(__OPENPIC_H__)
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#define __OPENPIC_H__
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/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
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enum {
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OPENPIC_OUTPUT_INT = 0, /* IRQ */
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OPENPIC_OUTPUT_CINT, /* critical IRQ */
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OPENPIC_OUTPUT_MCK, /* Machine check event */
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OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
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OPENPIC_OUTPUT_RESET, /* Core reset event */
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OPENPIC_OUTPUT_NB,
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};
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qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
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qemu_irq **irqs, qemu_irq irq_out);
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2009-10-02 05:12:16 +08:00
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qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
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2009-03-03 00:42:04 +08:00
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qemu_irq **irqs, qemu_irq irq_out);
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#endif /* __OPENPIC_H__ */
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