2005-03-13 17:43:36 +08:00
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/*
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* QEMU ESP emulation
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*
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2006-03-12 00:29:14 +08:00
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* Copyright (c) 2005-2006 Fabrice Bellard
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2005-03-13 17:43:36 +08:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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/* debug ESP card */
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2005-04-07 04:31:50 +08:00
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//#define DEBUG_ESP
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2005-03-13 17:43:36 +08:00
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#ifdef DEBUG_ESP
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#define DPRINTF(fmt, args...) \
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do { printf("ESP: " fmt , ##args); } while (0)
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2005-11-11 08:24:58 +08:00
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#define pic_set_irq(irq, level) \
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do { printf("ESP: set_irq(%d): %d\n", (irq), (level)); pic_set_irq((irq),(level));} while (0)
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2005-03-13 17:43:36 +08:00
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#else
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#define DPRINTF(fmt, args...)
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#endif
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#define ESPDMA_REGS 4
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#define ESPDMA_MAXADDR (ESPDMA_REGS * 4 - 1)
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#define ESP_MAXREG 0x3f
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2006-05-26 07:58:51 +08:00
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#define TI_BUFSZ 32
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2005-10-31 01:24:05 +08:00
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#define DMA_VER 0xa0000000
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2005-11-11 08:24:58 +08:00
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#define DMA_INTR 1
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#define DMA_INTREN 0x10
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2006-05-26 07:58:51 +08:00
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#define DMA_WRITE_MEM 0x100
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2005-10-31 01:24:05 +08:00
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#define DMA_LOADED 0x04000000
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2006-03-12 00:29:14 +08:00
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typedef struct ESPState ESPState;
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2005-03-13 17:43:36 +08:00
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2006-03-12 00:29:14 +08:00
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struct ESPState {
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2005-03-13 17:43:36 +08:00
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BlockDriverState **bd;
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2005-04-07 04:31:50 +08:00
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uint8_t rregs[ESP_MAXREG];
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uint8_t wregs[ESP_MAXREG];
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2005-03-13 17:43:36 +08:00
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int irq;
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uint32_t espdmaregs[ESPDMA_REGS];
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2005-04-07 04:31:50 +08:00
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uint32_t ti_size;
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2005-10-31 01:24:05 +08:00
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uint32_t ti_rptr, ti_wptr;
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uint8_t ti_buf[TI_BUFSZ];
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2006-05-27 05:53:41 +08:00
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int sense;
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2005-10-31 01:24:05 +08:00
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int dma;
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2006-05-26 07:58:51 +08:00
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SCSIDevice *scsi_dev[MAX_DISKS];
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SCSIDevice *current_dev;
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2006-06-03 22:19:19 +08:00
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uint8_t cmdbuf[TI_BUFSZ];
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int cmdlen;
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int do_cmd;
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2006-08-12 09:04:27 +08:00
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uint32_t dma_left;
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uint8_t async_buf[TARGET_PAGE_SIZE];
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uint32_t async_ptr;
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uint32_t async_len;
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2006-03-12 00:29:14 +08:00
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};
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2005-03-13 17:43:36 +08:00
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2005-04-07 04:31:50 +08:00
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#define STAT_DO 0x00
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#define STAT_DI 0x01
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#define STAT_CD 0x02
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#define STAT_ST 0x03
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#define STAT_MI 0x06
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#define STAT_MO 0x07
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#define STAT_TC 0x10
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2006-08-12 09:04:27 +08:00
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#define STAT_PE 0x20
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#define STAT_GE 0x40
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2005-04-07 04:31:50 +08:00
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#define STAT_IN 0x80
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#define INTR_FC 0x08
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#define INTR_BS 0x10
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#define INTR_DC 0x20
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2005-11-11 08:24:58 +08:00
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#define INTR_RST 0x80
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2005-04-07 04:31:50 +08:00
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#define SEQ_0 0x0
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#define SEQ_CD 0x4
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2006-06-03 22:19:19 +08:00
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static int get_cmd(ESPState *s, uint8_t *buf)
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2005-04-07 04:31:50 +08:00
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{
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uint32_t dmaptr, dmalen;
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int target;
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dmalen = s->wregs[0] | (s->wregs[1] << 8);
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2005-10-31 01:24:05 +08:00
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target = s->wregs[4] & 7;
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2006-06-03 22:19:19 +08:00
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DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
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2005-10-31 01:24:05 +08:00
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if (s->dma) {
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dmaptr = iommu_translate(s->espdmaregs[1]);
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2006-05-26 07:58:51 +08:00
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DPRINTF("DMA Direction: %c, addr 0x%8.8x\n",
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s->espdmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', dmaptr);
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2005-10-31 01:24:05 +08:00
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cpu_physical_memory_read(dmaptr, buf, dmalen);
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} else {
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buf[0] = 0;
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memcpy(&buf[1], s->ti_buf, dmalen);
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dmalen++;
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}
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2006-05-26 07:58:51 +08:00
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2005-04-07 04:31:50 +08:00
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s->ti_size = 0;
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2005-10-31 01:24:05 +08:00
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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2005-04-07 04:31:50 +08:00
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2006-05-26 07:58:51 +08:00
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if (target >= 4 || !s->scsi_dev[target]) {
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// No such drive
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2005-04-07 04:31:50 +08:00
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s->rregs[4] = STAT_IN;
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s->rregs[5] = INTR_DC;
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s->rregs[6] = SEQ_0;
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2005-11-11 08:24:58 +08:00
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s->espdmaregs[0] |= DMA_INTR;
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2005-04-07 04:31:50 +08:00
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pic_set_irq(s->irq, 1);
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2006-06-03 22:19:19 +08:00
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return 0;
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2005-04-07 04:31:50 +08:00
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}
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2006-05-26 07:58:51 +08:00
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s->current_dev = s->scsi_dev[target];
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2006-06-03 22:19:19 +08:00
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return dmalen;
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}
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static void do_cmd(ESPState *s, uint8_t *buf)
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{
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int32_t datalen;
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int lun;
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DPRINTF("do_cmd: busid 0x%x\n", buf[0]);
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lun = buf[0] & 7;
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2006-05-27 05:53:41 +08:00
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datalen = scsi_send_command(s->current_dev, 0, &buf[1], lun);
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2006-05-26 07:58:51 +08:00
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if (datalen == 0) {
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s->ti_size = 0;
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} else {
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s->rregs[4] = STAT_IN | STAT_TC;
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if (datalen > 0) {
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s->rregs[4] |= STAT_DI;
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s->ti_size = datalen;
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} else {
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s->rregs[4] |= STAT_DO;
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s->ti_size = -datalen;
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2005-12-06 04:30:36 +08:00
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}
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2005-04-07 04:31:50 +08:00
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}
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[6] = SEQ_CD;
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2005-11-11 08:24:58 +08:00
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s->espdmaregs[0] |= DMA_INTR;
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2005-04-07 04:31:50 +08:00
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pic_set_irq(s->irq, 1);
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}
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2006-06-03 22:19:19 +08:00
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static void handle_satn(ESPState *s)
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{
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uint8_t buf[32];
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int len;
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len = get_cmd(s, buf);
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if (len)
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do_cmd(s, buf);
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}
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static void handle_satn_stop(ESPState *s)
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{
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s->cmdlen = get_cmd(s, s->cmdbuf);
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if (s->cmdlen) {
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DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
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s->do_cmd = 1;
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s->espdmaregs[1] += s->cmdlen;
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s->rregs[4] = STAT_IN | STAT_TC | STAT_CD;
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[6] = SEQ_CD;
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s->espdmaregs[0] |= DMA_INTR;
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pic_set_irq(s->irq, 1);
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}
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}
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2006-05-27 05:53:41 +08:00
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static void write_response(ESPState *s)
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2005-04-07 04:31:50 +08:00
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{
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2006-05-21 20:46:31 +08:00
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uint32_t dmaptr;
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2005-04-07 04:31:50 +08:00
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2006-05-27 05:53:41 +08:00
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DPRINTF("Transfer status (sense=%d)\n", s->sense);
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s->ti_buf[0] = s->sense;
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s->ti_buf[1] = 0;
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2005-10-31 01:24:05 +08:00
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if (s->dma) {
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dmaptr = iommu_translate(s->espdmaregs[1]);
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2006-05-26 07:58:51 +08:00
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DPRINTF("DMA Direction: %c\n",
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s->espdmaregs[0] & DMA_WRITE_MEM ? 'w': 'r');
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2006-05-27 05:53:41 +08:00
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cpu_physical_memory_write(dmaptr, s->ti_buf, 2);
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2005-10-31 01:24:05 +08:00
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s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[6] = SEQ_CD;
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} else {
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2006-05-27 05:53:41 +08:00
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s->ti_size = 2;
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2005-10-31 01:24:05 +08:00
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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2006-05-27 05:53:41 +08:00
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s->rregs[7] = 2;
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2005-10-31 01:24:05 +08:00
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}
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2005-11-11 08:24:58 +08:00
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s->espdmaregs[0] |= DMA_INTR;
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2005-04-07 04:31:50 +08:00
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pic_set_irq(s->irq, 1);
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}
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2005-10-31 01:24:05 +08:00
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2006-08-12 09:04:27 +08:00
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static void esp_do_dma(ESPState *s)
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{
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uint32_t dmaptr, minlen, len, from, to;
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int to_device;
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to_device = (s->espdmaregs[0] & DMA_WRITE_MEM) == 0;
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from = s->espdmaregs[1];
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minlen = s->dma_left;
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to = from + minlen;
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dmaptr = iommu_translate(s->espdmaregs[1]);
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if ((from & TARGET_PAGE_MASK) != (to & TARGET_PAGE_MASK)) {
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len = TARGET_PAGE_SIZE - (from & ~TARGET_PAGE_MASK);
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} else {
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len = to - from;
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}
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DPRINTF("DMA address p %08x v %08x len %08x, from %08x, to %08x\n", dmaptr, s->espdmaregs[1], len, from, to);
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if (s->do_cmd) {
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2006-08-16 06:57:33 +08:00
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s->espdmaregs[1] += len;
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2006-08-12 09:04:27 +08:00
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s->ti_size -= len;
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DPRINTF("command len %d + %d\n", s->cmdlen, len);
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cpu_physical_memory_read(dmaptr, &s->cmdbuf[s->cmdlen], len);
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s->ti_size = 0;
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s->cmdlen = 0;
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s->do_cmd = 0;
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do_cmd(s, s->cmdbuf);
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return;
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} else {
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s->async_len = len;
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s->dma_left -= len;
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if (to_device) {
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s->async_ptr = -1;
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cpu_physical_memory_read(dmaptr, s->async_buf, len);
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scsi_write_data(s->current_dev, s->async_buf, len);
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} else {
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s->async_ptr = dmaptr;
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scsi_read_data(s->current_dev, s->async_buf, len);
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}
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}
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}
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static void esp_command_complete(void *opaque, uint32_t reason, int sense)
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2006-05-26 07:58:51 +08:00
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{
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ESPState *s = (ESPState *)opaque;
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2006-08-12 09:04:27 +08:00
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s->ti_size -= s->async_len;
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s->espdmaregs[1] += s->async_len;
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if (s->async_ptr != (uint32_t)-1) {
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cpu_physical_memory_write(s->async_ptr, s->async_buf, s->async_len);
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}
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if (reason == SCSI_REASON_DONE) {
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DPRINTF("SCSI Command complete\n");
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if (s->ti_size != 0)
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DPRINTF("SCSI command completed unexpectedly\n");
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s->ti_size = 0;
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if (sense)
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DPRINTF("Command failed\n");
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s->sense = sense;
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} else {
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DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
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}
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if (s->dma_left) {
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esp_do_dma(s);
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} else {
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if (s->ti_size) {
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s->rregs[4] |= STAT_IN | STAT_TC;
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} else {
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s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
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}
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s->rregs[5] = INTR_BS;
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s->rregs[6] = 0;
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s->rregs[7] = 0;
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s->espdmaregs[0] |= DMA_INTR;
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pic_set_irq(s->irq, 1);
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}
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2006-05-26 07:58:51 +08:00
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}
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2005-04-07 04:31:50 +08:00
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static void handle_ti(ESPState *s)
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{
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2006-08-12 09:04:27 +08:00
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uint32_t dmalen, minlen;
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2005-04-07 04:31:50 +08:00
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dmalen = s->wregs[0] | (s->wregs[1] << 8);
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2006-05-21 20:46:31 +08:00
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if (dmalen==0) {
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dmalen=0x10000;
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}
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2006-06-03 22:19:19 +08:00
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if (s->do_cmd)
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minlen = (dmalen < 32) ? dmalen : 32;
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else
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minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
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2006-05-21 20:46:31 +08:00
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DPRINTF("Transfer Information len %d\n", minlen);
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2005-10-31 01:24:05 +08:00
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if (s->dma) {
|
2006-08-12 09:04:27 +08:00
|
|
|
s->dma_left = minlen;
|
|
|
|
s->rregs[4] &= ~STAT_TC;
|
|
|
|
esp_do_dma(s);
|
2006-06-03 22:19:19 +08:00
|
|
|
} else if (s->do_cmd) {
|
|
|
|
DPRINTF("command len %d\n", s->cmdlen);
|
|
|
|
s->ti_size = 0;
|
|
|
|
s->cmdlen = 0;
|
|
|
|
s->do_cmd = 0;
|
|
|
|
do_cmd(s, s->cmdbuf);
|
|
|
|
return;
|
|
|
|
}
|
2005-04-07 04:31:50 +08:00
|
|
|
}
|
|
|
|
|
2005-03-13 17:43:36 +08:00
|
|
|
static void esp_reset(void *opaque)
|
|
|
|
{
|
|
|
|
ESPState *s = opaque;
|
2005-04-07 04:31:50 +08:00
|
|
|
memset(s->rregs, 0, ESP_MAXREG);
|
2006-03-12 00:29:14 +08:00
|
|
|
memset(s->wregs, 0, ESP_MAXREG);
|
2005-04-07 04:31:50 +08:00
|
|
|
s->rregs[0x0e] = 0x4; // Indicate fas100a
|
2005-03-13 17:43:36 +08:00
|
|
|
memset(s->espdmaregs, 0, ESPDMA_REGS * 4);
|
2006-03-12 00:29:14 +08:00
|
|
|
s->ti_size = 0;
|
|
|
|
s->ti_rptr = 0;
|
|
|
|
s->ti_wptr = 0;
|
|
|
|
s->dma = 0;
|
2006-06-03 22:19:19 +08:00
|
|
|
s->do_cmd = 0;
|
2005-03-13 17:43:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
ESPState *s = opaque;
|
|
|
|
uint32_t saddr;
|
|
|
|
|
|
|
|
saddr = (addr & ESP_MAXREG) >> 2;
|
2005-11-11 08:24:58 +08:00
|
|
|
DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
|
2005-03-13 17:43:36 +08:00
|
|
|
switch (saddr) {
|
2005-10-31 01:24:05 +08:00
|
|
|
case 2:
|
|
|
|
// FIFO
|
|
|
|
if (s->ti_size > 0) {
|
|
|
|
s->ti_size--;
|
2006-05-26 07:58:51 +08:00
|
|
|
if ((s->rregs[4] & 6) == 0) {
|
|
|
|
/* Data in/out. */
|
|
|
|
scsi_read_data(s->current_dev, &s->rregs[2], 0);
|
|
|
|
} else {
|
|
|
|
s->rregs[2] = s->ti_buf[s->ti_rptr++];
|
|
|
|
}
|
2005-10-31 01:24:05 +08:00
|
|
|
pic_set_irq(s->irq, 1);
|
|
|
|
}
|
|
|
|
if (s->ti_size == 0) {
|
|
|
|
s->ti_rptr = 0;
|
|
|
|
s->ti_wptr = 0;
|
|
|
|
}
|
|
|
|
break;
|
2005-11-11 08:24:58 +08:00
|
|
|
case 5:
|
|
|
|
// interrupt
|
2006-08-12 09:04:27 +08:00
|
|
|
// Clear interrupt/error status bits
|
|
|
|
s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE);
|
2005-11-11 08:24:58 +08:00
|
|
|
pic_set_irq(s->irq, 0);
|
|
|
|
s->espdmaregs[0] &= ~DMA_INTR;
|
|
|
|
break;
|
2005-03-13 17:43:36 +08:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2005-04-07 04:31:50 +08:00
|
|
|
return s->rregs[saddr];
|
2005-03-13 17:43:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
|
|
{
|
|
|
|
ESPState *s = opaque;
|
|
|
|
uint32_t saddr;
|
|
|
|
|
|
|
|
saddr = (addr & ESP_MAXREG) >> 2;
|
2005-04-07 04:31:50 +08:00
|
|
|
DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], val);
|
2005-03-13 17:43:36 +08:00
|
|
|
switch (saddr) {
|
2005-10-31 01:24:05 +08:00
|
|
|
case 0:
|
|
|
|
case 1:
|
|
|
|
s->rregs[saddr] = val;
|
2006-08-12 09:04:27 +08:00
|
|
|
s->rregs[4] &= ~STAT_TC;
|
2005-10-31 01:24:05 +08:00
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
// FIFO
|
2006-06-03 22:19:19 +08:00
|
|
|
if (s->do_cmd) {
|
|
|
|
s->cmdbuf[s->cmdlen++] = val & 0xff;
|
|
|
|
} else if ((s->rregs[4] & 6) == 0) {
|
2006-05-26 07:58:51 +08:00
|
|
|
uint8_t buf;
|
|
|
|
buf = val & 0xff;
|
|
|
|
s->ti_size--;
|
|
|
|
scsi_write_data(s->current_dev, &buf, 0);
|
|
|
|
} else {
|
|
|
|
s->ti_size++;
|
|
|
|
s->ti_buf[s->ti_wptr++] = val & 0xff;
|
|
|
|
}
|
2005-10-31 01:24:05 +08:00
|
|
|
break;
|
2005-03-13 17:43:36 +08:00
|
|
|
case 3:
|
2005-10-31 01:24:05 +08:00
|
|
|
s->rregs[saddr] = val;
|
2005-03-13 17:43:36 +08:00
|
|
|
// Command
|
2005-10-31 01:24:05 +08:00
|
|
|
if (val & 0x80) {
|
|
|
|
s->dma = 1;
|
|
|
|
} else {
|
|
|
|
s->dma = 0;
|
|
|
|
}
|
2005-03-13 17:43:36 +08:00
|
|
|
switch(val & 0x7f) {
|
|
|
|
case 0:
|
2005-04-07 04:31:50 +08:00
|
|
|
DPRINTF("NOP (%2.2x)\n", val);
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
DPRINTF("Flush FIFO (%2.2x)\n", val);
|
2005-11-11 08:24:58 +08:00
|
|
|
//s->ti_size = 0;
|
2005-04-07 04:31:50 +08:00
|
|
|
s->rregs[5] = INTR_FC;
|
2005-11-11 08:24:58 +08:00
|
|
|
s->rregs[6] = 0;
|
2005-03-13 17:43:36 +08:00
|
|
|
break;
|
|
|
|
case 2:
|
2005-04-07 04:31:50 +08:00
|
|
|
DPRINTF("Chip reset (%2.2x)\n", val);
|
2005-03-13 17:43:36 +08:00
|
|
|
esp_reset(s);
|
|
|
|
break;
|
|
|
|
case 3:
|
2005-04-07 04:31:50 +08:00
|
|
|
DPRINTF("Bus reset (%2.2x)\n", val);
|
2005-11-11 08:24:58 +08:00
|
|
|
s->rregs[5] = INTR_RST;
|
|
|
|
if (!(s->wregs[8] & 0x40)) {
|
|
|
|
s->espdmaregs[0] |= DMA_INTR;
|
|
|
|
pic_set_irq(s->irq, 1);
|
|
|
|
}
|
2005-04-07 04:31:50 +08:00
|
|
|
break;
|
|
|
|
case 0x10:
|
|
|
|
handle_ti(s);
|
|
|
|
break;
|
|
|
|
case 0x11:
|
|
|
|
DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
|
2006-05-27 05:53:41 +08:00
|
|
|
write_response(s);
|
2005-04-07 04:31:50 +08:00
|
|
|
break;
|
|
|
|
case 0x12:
|
|
|
|
DPRINTF("Message Accepted (%2.2x)\n", val);
|
2006-05-27 05:53:41 +08:00
|
|
|
write_response(s);
|
2005-04-07 04:31:50 +08:00
|
|
|
s->rregs[5] = INTR_DC;
|
|
|
|
s->rregs[6] = 0;
|
2005-03-13 17:43:36 +08:00
|
|
|
break;
|
|
|
|
case 0x1a:
|
2005-04-07 04:31:50 +08:00
|
|
|
DPRINTF("Set ATN (%2.2x)\n", val);
|
2005-03-13 17:43:36 +08:00
|
|
|
break;
|
|
|
|
case 0x42:
|
2006-06-03 22:19:19 +08:00
|
|
|
DPRINTF("Set ATN (%2.2x)\n", val);
|
2005-04-07 04:31:50 +08:00
|
|
|
handle_satn(s);
|
|
|
|
break;
|
|
|
|
case 0x43:
|
|
|
|
DPRINTF("Set ATN & stop (%2.2x)\n", val);
|
2006-06-03 22:19:19 +08:00
|
|
|
handle_satn_stop(s);
|
2005-04-07 04:31:50 +08:00
|
|
|
break;
|
|
|
|
default:
|
2005-10-31 01:24:05 +08:00
|
|
|
DPRINTF("Unhandled ESP command (%2.2x)\n", val);
|
2005-03-13 17:43:36 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 4 ... 7:
|
|
|
|
break;
|
2005-10-31 01:24:05 +08:00
|
|
|
case 8:
|
|
|
|
s->rregs[saddr] = val;
|
|
|
|
break;
|
|
|
|
case 9 ... 10:
|
|
|
|
break;
|
2005-11-11 08:24:58 +08:00
|
|
|
case 11:
|
|
|
|
s->rregs[saddr] = val & 0x15;
|
|
|
|
break;
|
|
|
|
case 12 ... 15:
|
2005-10-31 01:24:05 +08:00
|
|
|
s->rregs[saddr] = val;
|
|
|
|
break;
|
2005-03-13 17:43:36 +08:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2005-04-07 04:31:50 +08:00
|
|
|
s->wregs[saddr] = val;
|
2005-03-13 17:43:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static CPUReadMemoryFunc *esp_mem_read[3] = {
|
|
|
|
esp_mem_readb,
|
|
|
|
esp_mem_readb,
|
|
|
|
esp_mem_readb,
|
|
|
|
};
|
|
|
|
|
|
|
|
static CPUWriteMemoryFunc *esp_mem_write[3] = {
|
|
|
|
esp_mem_writeb,
|
|
|
|
esp_mem_writeb,
|
|
|
|
esp_mem_writeb,
|
|
|
|
};
|
|
|
|
|
|
|
|
static uint32_t espdma_mem_readl(void *opaque, target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
ESPState *s = opaque;
|
|
|
|
uint32_t saddr;
|
|
|
|
|
|
|
|
saddr = (addr & ESPDMA_MAXADDR) >> 2;
|
2005-10-31 01:24:05 +08:00
|
|
|
DPRINTF("read dmareg[%d]: 0x%8.8x\n", saddr, s->espdmaregs[saddr]);
|
|
|
|
|
2005-03-13 17:43:36 +08:00
|
|
|
return s->espdmaregs[saddr];
|
|
|
|
}
|
|
|
|
|
|
|
|
static void espdma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
|
|
{
|
|
|
|
ESPState *s = opaque;
|
|
|
|
uint32_t saddr;
|
|
|
|
|
|
|
|
saddr = (addr & ESPDMA_MAXADDR) >> 2;
|
2005-10-31 01:24:05 +08:00
|
|
|
DPRINTF("write dmareg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->espdmaregs[saddr], val);
|
2005-04-07 04:31:50 +08:00
|
|
|
switch (saddr) {
|
|
|
|
case 0:
|
2005-11-11 08:24:58 +08:00
|
|
|
if (!(val & DMA_INTREN))
|
2005-04-07 04:31:50 +08:00
|
|
|
pic_set_irq(s->irq, 0);
|
2005-10-31 01:24:05 +08:00
|
|
|
if (val & 0x80) {
|
|
|
|
esp_reset(s);
|
|
|
|
} else if (val & 0x40) {
|
|
|
|
val &= ~0x40;
|
|
|
|
} else if (val == 0)
|
|
|
|
val = 0x40;
|
|
|
|
val &= 0x0fffffff;
|
|
|
|
val |= DMA_VER;
|
2005-04-07 04:31:50 +08:00
|
|
|
break;
|
2005-10-31 01:24:05 +08:00
|
|
|
case 1:
|
2006-05-22 06:20:03 +08:00
|
|
|
s->espdmaregs[0] |= DMA_LOADED;
|
2005-10-31 01:24:05 +08:00
|
|
|
break;
|
2005-04-07 04:31:50 +08:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2005-03-13 17:43:36 +08:00
|
|
|
s->espdmaregs[saddr] = val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static CPUReadMemoryFunc *espdma_mem_read[3] = {
|
|
|
|
espdma_mem_readl,
|
|
|
|
espdma_mem_readl,
|
|
|
|
espdma_mem_readl,
|
|
|
|
};
|
|
|
|
|
|
|
|
static CPUWriteMemoryFunc *espdma_mem_write[3] = {
|
|
|
|
espdma_mem_writel,
|
|
|
|
espdma_mem_writel,
|
|
|
|
espdma_mem_writel,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void esp_save(QEMUFile *f, void *opaque)
|
|
|
|
{
|
|
|
|
ESPState *s = opaque;
|
2005-04-07 04:31:50 +08:00
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
qemu_put_buffer(f, s->rregs, ESP_MAXREG);
|
|
|
|
qemu_put_buffer(f, s->wregs, ESP_MAXREG);
|
|
|
|
qemu_put_be32s(f, &s->irq);
|
|
|
|
for (i = 0; i < ESPDMA_REGS; i++)
|
|
|
|
qemu_put_be32s(f, &s->espdmaregs[i]);
|
2005-10-31 01:24:05 +08:00
|
|
|
qemu_put_be32s(f, &s->ti_size);
|
|
|
|
qemu_put_be32s(f, &s->ti_rptr);
|
|
|
|
qemu_put_be32s(f, &s->ti_wptr);
|
|
|
|
qemu_put_buffer(f, s->ti_buf, TI_BUFSZ);
|
|
|
|
qemu_put_be32s(f, &s->dma);
|
2005-03-13 17:43:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int esp_load(QEMUFile *f, void *opaque, int version_id)
|
|
|
|
{
|
|
|
|
ESPState *s = opaque;
|
2005-04-07 04:31:50 +08:00
|
|
|
unsigned int i;
|
2005-03-13 17:43:36 +08:00
|
|
|
|
|
|
|
if (version_id != 1)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2005-04-07 04:31:50 +08:00
|
|
|
qemu_get_buffer(f, s->rregs, ESP_MAXREG);
|
|
|
|
qemu_get_buffer(f, s->wregs, ESP_MAXREG);
|
|
|
|
qemu_get_be32s(f, &s->irq);
|
|
|
|
for (i = 0; i < ESPDMA_REGS; i++)
|
|
|
|
qemu_get_be32s(f, &s->espdmaregs[i]);
|
2005-10-31 01:24:05 +08:00
|
|
|
qemu_get_be32s(f, &s->ti_size);
|
|
|
|
qemu_get_be32s(f, &s->ti_rptr);
|
|
|
|
qemu_get_be32s(f, &s->ti_wptr);
|
|
|
|
qemu_get_buffer(f, s->ti_buf, TI_BUFSZ);
|
|
|
|
qemu_get_be32s(f, &s->dma);
|
2005-04-07 04:31:50 +08:00
|
|
|
|
2005-03-13 17:43:36 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void esp_init(BlockDriverState **bd, int irq, uint32_t espaddr, uint32_t espdaddr)
|
|
|
|
{
|
|
|
|
ESPState *s;
|
|
|
|
int esp_io_memory, espdma_io_memory;
|
2006-05-26 07:58:51 +08:00
|
|
|
int i;
|
2005-03-13 17:43:36 +08:00
|
|
|
|
|
|
|
s = qemu_mallocz(sizeof(ESPState));
|
|
|
|
if (!s)
|
|
|
|
return;
|
|
|
|
|
|
|
|
s->bd = bd;
|
|
|
|
s->irq = irq;
|
|
|
|
|
|
|
|
esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
|
|
|
|
cpu_register_physical_memory(espaddr, ESP_MAXREG*4, esp_io_memory);
|
|
|
|
|
|
|
|
espdma_io_memory = cpu_register_io_memory(0, espdma_mem_read, espdma_mem_write, s);
|
|
|
|
cpu_register_physical_memory(espdaddr, 16, espdma_io_memory);
|
|
|
|
|
|
|
|
esp_reset(s);
|
|
|
|
|
|
|
|
register_savevm("esp", espaddr, 1, esp_save, esp_load, s);
|
|
|
|
qemu_register_reset(esp_reset, s);
|
2006-05-26 07:58:51 +08:00
|
|
|
for (i = 0; i < MAX_DISKS; i++) {
|
|
|
|
if (bs_table[i]) {
|
|
|
|
s->scsi_dev[i] =
|
|
|
|
scsi_disk_init(bs_table[i], esp_command_complete, s);
|
|
|
|
}
|
|
|
|
}
|
2005-03-13 17:43:36 +08:00
|
|
|
}
|
|
|
|
|