2014-01-31 06:02:06 +08:00
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/*
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* Emulation of Allwinner EMAC Fast Ethernet controller and
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* Realtek RTL8201CP PHY
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*
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* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
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*
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* This model is based on reverse-engineering of Linux kernel driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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2016-01-27 02:17:05 +08:00
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#include "qemu/osdep.h"
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2014-01-31 06:02:06 +08:00
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#include "hw/sysbus.h"
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#include "net/net.h"
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#include "qemu/fifo8.h"
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#include "hw/net/allwinner_emac.h"
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2015-12-15 20:16:16 +08:00
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#include "qemu/log.h"
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2014-01-31 06:02:06 +08:00
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#include <zlib.h>
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static uint8_t padding[60];
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static void mii_set_link(RTL8201CPState *mii, bool link_ok)
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{
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if (link_ok) {
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2014-03-26 02:22:09 +08:00
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mii->bmsr |= MII_BMSR_LINK_ST | MII_BMSR_AN_COMP;
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2014-01-31 06:02:06 +08:00
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mii->anlpar |= MII_ANAR_TXFD | MII_ANAR_10FD | MII_ANAR_10 |
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MII_ANAR_CSMACD;
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} else {
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2014-03-26 02:22:09 +08:00
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mii->bmsr &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP);
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2014-01-31 06:02:06 +08:00
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mii->anlpar = MII_ANAR_TX;
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}
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}
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static void mii_reset(RTL8201CPState *mii, bool link_ok)
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{
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mii->bmcr = MII_BMCR_FD | MII_BMCR_AUTOEN | MII_BMCR_SPEED;
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mii->bmsr = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD |
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MII_BMSR_10T_HD | MII_BMSR_MFPS | MII_BMSR_AUTONEG;
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mii->anar = MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD | MII_ANAR_10 |
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MII_ANAR_CSMACD;
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mii->anlpar = MII_ANAR_TX;
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mii_set_link(mii, link_ok);
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}
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static uint16_t RTL8201CP_mdio_read(AwEmacState *s, uint8_t addr, uint8_t reg)
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{
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RTL8201CPState *mii = &s->mii;
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uint16_t ret = 0xffff;
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if (addr == s->phy_addr) {
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switch (reg) {
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case MII_BMCR:
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return mii->bmcr;
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case MII_BMSR:
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return mii->bmsr;
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case MII_PHYID1:
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return RTL8201CP_PHYID1;
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case MII_PHYID2:
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return RTL8201CP_PHYID2;
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case MII_ANAR:
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return mii->anar;
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case MII_ANLPAR:
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return mii->anlpar;
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case MII_ANER:
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case MII_NSR:
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case MII_LBREMR:
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case MII_REC:
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case MII_SNRDR:
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case MII_TEST:
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qemu_log_mask(LOG_UNIMP,
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"allwinner_emac: read from unimpl. mii reg 0x%x\n",
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reg);
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return 0;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"allwinner_emac: read from invalid mii reg 0x%x\n",
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reg);
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return 0;
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}
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}
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return ret;
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}
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static void RTL8201CP_mdio_write(AwEmacState *s, uint8_t addr, uint8_t reg,
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uint16_t value)
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{
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RTL8201CPState *mii = &s->mii;
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NetClientState *nc;
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if (addr == s->phy_addr) {
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switch (reg) {
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case MII_BMCR:
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if (value & MII_BMCR_RESET) {
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nc = qemu_get_queue(s->nic);
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mii_reset(mii, !nc->link_down);
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} else {
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mii->bmcr = value;
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}
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break;
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case MII_ANAR:
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mii->anar = value;
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break;
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case MII_BMSR:
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case MII_PHYID1:
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case MII_PHYID2:
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case MII_ANLPAR:
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case MII_ANER:
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qemu_log_mask(LOG_GUEST_ERROR,
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"allwinner_emac: write to read-only mii reg 0x%x\n",
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reg);
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break;
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case MII_NSR:
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case MII_LBREMR:
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case MII_REC:
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case MII_SNRDR:
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case MII_TEST:
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qemu_log_mask(LOG_UNIMP,
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"allwinner_emac: write to unimpl. mii reg 0x%x\n",
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reg);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"allwinner_emac: write to invalid mii reg 0x%x\n",
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reg);
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}
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}
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}
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static void aw_emac_update_irq(AwEmacState *s)
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{
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qemu_set_irq(s->irq, (s->int_sta & s->int_ctl) != 0);
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}
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static void aw_emac_tx_reset(AwEmacState *s, int chan)
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{
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fifo8_reset(&s->tx_fifo[chan]);
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s->tx_length[chan] = 0;
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}
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static void aw_emac_rx_reset(AwEmacState *s)
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{
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fifo8_reset(&s->rx_fifo);
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s->rx_num_packets = 0;
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s->rx_packet_size = 0;
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s->rx_packet_pos = 0;
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}
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static void fifo8_push_word(Fifo8 *fifo, uint32_t val)
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{
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fifo8_push(fifo, val);
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fifo8_push(fifo, val >> 8);
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fifo8_push(fifo, val >> 16);
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fifo8_push(fifo, val >> 24);
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}
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static uint32_t fifo8_pop_word(Fifo8 *fifo)
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{
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uint32_t ret;
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ret = fifo8_pop(fifo);
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ret |= fifo8_pop(fifo) << 8;
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ret |= fifo8_pop(fifo) << 16;
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ret |= fifo8_pop(fifo) << 24;
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return ret;
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}
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static int aw_emac_can_receive(NetClientState *nc)
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{
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AwEmacState *s = qemu_get_nic_opaque(nc);
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/*
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* To avoid packet drops, allow reception only when there is space
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* for a full frame: 1522 + 8 (rx headers) + 2 (padding).
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*/
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return (s->ctl & EMAC_CTL_RX_EN) && (fifo8_num_free(&s->rx_fifo) >= 1532);
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}
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static ssize_t aw_emac_receive(NetClientState *nc, const uint8_t *buf,
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size_t size)
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{
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AwEmacState *s = qemu_get_nic_opaque(nc);
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Fifo8 *fifo = &s->rx_fifo;
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size_t padded_size, total_size;
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uint32_t crc;
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padded_size = size > 60 ? size : 60;
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total_size = QEMU_ALIGN_UP(RX_HDR_SIZE + padded_size + CRC_SIZE, 4);
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if (!(s->ctl & EMAC_CTL_RX_EN) || (fifo8_num_free(fifo) < total_size)) {
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return -1;
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}
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fifo8_push_word(fifo, EMAC_UNDOCUMENTED_MAGIC);
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fifo8_push_word(fifo, EMAC_RX_HEADER(padded_size + CRC_SIZE,
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EMAC_RX_IO_DATA_STATUS_OK));
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fifo8_push_all(fifo, buf, size);
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crc = crc32(~0, buf, size);
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if (padded_size != size) {
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fifo8_push_all(fifo, padding, padded_size - size);
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crc = crc32(crc, padding, padded_size - size);
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}
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fifo8_push_word(fifo, crc);
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fifo8_push_all(fifo, padding, QEMU_ALIGN_UP(padded_size, 4) - padded_size);
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s->rx_num_packets++;
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s->int_sta |= EMAC_INT_RX;
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aw_emac_update_irq(s);
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return size;
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}
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static void aw_emac_reset(DeviceState *dev)
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{
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AwEmacState *s = AW_EMAC(dev);
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NetClientState *nc = qemu_get_queue(s->nic);
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s->ctl = 0;
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s->tx_mode = 0;
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s->int_ctl = 0;
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s->int_sta = 0;
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s->tx_channel = 0;
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s->phy_target = 0;
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aw_emac_tx_reset(s, 0);
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aw_emac_tx_reset(s, 1);
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aw_emac_rx_reset(s);
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mii_reset(&s->mii, !nc->link_down);
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}
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static uint64_t aw_emac_read(void *opaque, hwaddr offset, unsigned size)
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{
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AwEmacState *s = opaque;
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Fifo8 *fifo = &s->rx_fifo;
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NetClientState *nc;
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uint64_t ret;
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switch (offset) {
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case EMAC_CTL_REG:
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return s->ctl;
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case EMAC_TX_MODE_REG:
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return s->tx_mode;
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case EMAC_TX_INS_REG:
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return s->tx_channel;
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case EMAC_RX_CTL_REG:
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return s->rx_ctl;
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case EMAC_RX_IO_DATA_REG:
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if (!s->rx_num_packets) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Read IO data register when no packet available");
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return 0;
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}
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ret = fifo8_pop_word(fifo);
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switch (s->rx_packet_pos) {
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case 0: /* Word is magic header */
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s->rx_packet_pos += 4;
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break;
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case 4: /* Word is rx info header */
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s->rx_packet_pos += 4;
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s->rx_packet_size = QEMU_ALIGN_UP(extract32(ret, 0, 16), 4);
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break;
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default: /* Word is packet data */
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s->rx_packet_pos += 4;
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s->rx_packet_size -= 4;
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if (!s->rx_packet_size) {
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s->rx_packet_pos = 0;
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s->rx_num_packets--;
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nc = qemu_get_queue(s->nic);
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if (aw_emac_can_receive(nc)) {
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qemu_flush_queued_packets(nc);
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}
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}
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}
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return ret;
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case EMAC_RX_FBC_REG:
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return s->rx_num_packets;
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case EMAC_INT_CTL_REG:
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return s->int_ctl;
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case EMAC_INT_STA_REG:
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return s->int_sta;
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case EMAC_MAC_MRDD_REG:
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return RTL8201CP_mdio_read(s,
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extract32(s->phy_target, PHY_ADDR_SHIFT, 8),
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extract32(s->phy_target, PHY_REG_SHIFT, 8));
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default:
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qemu_log_mask(LOG_UNIMP,
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"allwinner_emac: read access to unknown register 0x"
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TARGET_FMT_plx "\n", offset);
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ret = 0;
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}
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return ret;
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}
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static void aw_emac_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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AwEmacState *s = opaque;
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Fifo8 *fifo;
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NetClientState *nc = qemu_get_queue(s->nic);
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int chan;
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switch (offset) {
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case EMAC_CTL_REG:
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if (value & EMAC_CTL_RESET) {
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aw_emac_reset(DEVICE(s));
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value &= ~EMAC_CTL_RESET;
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}
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s->ctl = value;
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if (aw_emac_can_receive(nc)) {
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qemu_flush_queued_packets(nc);
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}
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break;
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case EMAC_TX_MODE_REG:
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s->tx_mode = value;
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break;
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case EMAC_TX_CTL0_REG:
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case EMAC_TX_CTL1_REG:
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chan = (offset == EMAC_TX_CTL0_REG ? 0 : 1);
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if ((value & 1) && (s->ctl & EMAC_CTL_TX_EN)) {
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uint32_t len, ret;
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const uint8_t *data;
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fifo = &s->tx_fifo[chan];
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len = s->tx_length[chan];
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if (len > fifo8_num_used(fifo)) {
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len = fifo8_num_used(fifo);
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qemu_log_mask(LOG_GUEST_ERROR,
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"allwinner_emac: TX length > fifo data length\n");
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}
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if (len > 0) {
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data = fifo8_pop_buf(fifo, len, &ret);
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qemu_send_packet(nc, data, ret);
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aw_emac_tx_reset(s, chan);
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/* Raise TX interrupt */
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s->int_sta |= EMAC_INT_TX_CHAN(chan);
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|
aw_emac_update_irq(s);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case EMAC_TX_INS_REG:
|
|
|
|
s->tx_channel = value < NUM_TX_FIFOS ? value : 0;
|
|
|
|
break;
|
|
|
|
case EMAC_TX_PL0_REG:
|
|
|
|
case EMAC_TX_PL1_REG:
|
|
|
|
chan = (offset == EMAC_TX_PL0_REG ? 0 : 1);
|
|
|
|
if (value > TX_FIFO_SIZE) {
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"allwinner_emac: invalid TX frame length %d\n",
|
|
|
|
(int)value);
|
|
|
|
value = TX_FIFO_SIZE;
|
|
|
|
}
|
|
|
|
s->tx_length[chan] = value;
|
|
|
|
break;
|
|
|
|
case EMAC_TX_IO_DATA_REG:
|
|
|
|
fifo = &s->tx_fifo[s->tx_channel];
|
|
|
|
if (fifo8_num_free(fifo) < 4) {
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"allwinner_emac: TX data overruns fifo\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
fifo8_push_word(fifo, value);
|
|
|
|
break;
|
|
|
|
case EMAC_RX_CTL_REG:
|
|
|
|
s->rx_ctl = value;
|
|
|
|
break;
|
|
|
|
case EMAC_RX_FBC_REG:
|
|
|
|
if (value == 0) {
|
|
|
|
aw_emac_rx_reset(s);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case EMAC_INT_CTL_REG:
|
|
|
|
s->int_ctl = value;
|
2014-03-26 02:22:10 +08:00
|
|
|
aw_emac_update_irq(s);
|
2014-01-31 06:02:06 +08:00
|
|
|
break;
|
|
|
|
case EMAC_INT_STA_REG:
|
|
|
|
s->int_sta &= ~value;
|
2014-03-26 02:22:10 +08:00
|
|
|
aw_emac_update_irq(s);
|
2014-01-31 06:02:06 +08:00
|
|
|
break;
|
|
|
|
case EMAC_MAC_MADR_REG:
|
|
|
|
s->phy_target = value;
|
|
|
|
break;
|
|
|
|
case EMAC_MAC_MWTD_REG:
|
|
|
|
RTL8201CP_mdio_write(s, extract32(s->phy_target, PHY_ADDR_SHIFT, 8),
|
|
|
|
extract32(s->phy_target, PHY_REG_SHIFT, 8), value);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
qemu_log_mask(LOG_UNIMP,
|
|
|
|
"allwinner_emac: write access to unknown register 0x"
|
|
|
|
TARGET_FMT_plx "\n", offset);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aw_emac_set_link(NetClientState *nc)
|
|
|
|
{
|
|
|
|
AwEmacState *s = qemu_get_nic_opaque(nc);
|
|
|
|
|
|
|
|
mii_set_link(&s->mii, !nc->link_down);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps aw_emac_mem_ops = {
|
|
|
|
.read = aw_emac_read,
|
|
|
|
.write = aw_emac_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static NetClientInfo net_aw_emac_info = {
|
qapi: Change Netdev into a flat union
This is a mostly-mechanical conversion that creates a new flat
union 'Netdev' QAPI type that covers all the branches of the
former 'NetClientOptions' simple union, where the branches are
now listed in a new 'NetClientDriver' enum rather than generated
from the simple union. The existence of a flat union has no
change to the command line syntax accepted for new code, and
will make it possible for a future patch to switch the QMP
command to parse a boxed union for no change to valid QMP; but
it does have some ripple effect on the C code when dealing with
the new types.
While making the conversion, note that the 'NetLegacy' type
remains unchanged: it applies only to legacy command line options,
and will not be ported to QMP, so it should remain a wrapper
around a simple union; to avoid confusion, the type named
'NetClientOptions' is now gone, and we introduce 'NetLegacyOptions'
in its place. Then, in the C code, we convert from NetLegacy to
Netdev as soon as possible, so that the bulk of the net stack
only has to deal with one QAPI type, not two. Note that since
the old legacy code always rejected 'hubport', we can just omit
that branch from the new 'NetLegacyOptions' simple union.
Based on an idea originally by Zoltán Kővágó <DirtY.iCE.hu@gmail.com>:
Message-Id: <01a527fbf1a5de880091f98cf011616a78adeeee.1441627176.git.DirtY.iCE.hu@gmail.com>
although the sed script in that patch no longer applies due to
other changes in the tree since then, and I also did some manual
cleanups (such as fixing whitespace to keep checkpatch happy).
Signed-off-by: Eric Blake <eblake@redhat.com>
Message-Id: <1468468228-27827-13-git-send-email-eblake@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Fixup from Eric squashed in]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-07-14 11:50:23 +08:00
|
|
|
.type = NET_CLIENT_DRIVER_NIC,
|
2014-01-31 06:02:06 +08:00
|
|
|
.size = sizeof(NICState),
|
|
|
|
.can_receive = aw_emac_can_receive,
|
|
|
|
.receive = aw_emac_receive,
|
|
|
|
.link_status_changed = aw_emac_set_link,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void aw_emac_init(Object *obj)
|
|
|
|
{
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
|
|
AwEmacState *s = AW_EMAC(obj);
|
|
|
|
|
|
|
|
memory_region_init_io(&s->iomem, OBJECT(s), &aw_emac_mem_ops, s,
|
|
|
|
"aw_emac", 0x1000);
|
|
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aw_emac_realize(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
AwEmacState *s = AW_EMAC(dev);
|
|
|
|
|
|
|
|
qemu_macaddr_default_if_unset(&s->conf.macaddr);
|
|
|
|
s->nic = qemu_new_nic(&net_aw_emac_info, &s->conf,
|
|
|
|
object_get_typename(OBJECT(dev)), dev->id, s);
|
|
|
|
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
|
|
|
|
|
|
|
|
fifo8_create(&s->rx_fifo, RX_FIFO_SIZE);
|
|
|
|
fifo8_create(&s->tx_fifo[0], TX_FIFO_SIZE);
|
|
|
|
fifo8_create(&s->tx_fifo[1], TX_FIFO_SIZE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static Property aw_emac_properties[] = {
|
|
|
|
DEFINE_NIC_PROPERTIES(AwEmacState, conf),
|
|
|
|
DEFINE_PROP_UINT8("phy-addr", AwEmacState, phy_addr, 0),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_mii = {
|
|
|
|
.name = "rtl8201cp",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT16(bmcr, RTL8201CPState),
|
|
|
|
VMSTATE_UINT16(bmsr, RTL8201CPState),
|
|
|
|
VMSTATE_UINT16(anar, RTL8201CPState),
|
|
|
|
VMSTATE_UINT16(anlpar, RTL8201CPState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static int aw_emac_post_load(void *opaque, int version_id)
|
|
|
|
{
|
|
|
|
AwEmacState *s = opaque;
|
|
|
|
|
|
|
|
aw_emac_set_link(qemu_get_queue(s->nic));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_aw_emac = {
|
|
|
|
.name = "allwinner_emac",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.post_load = aw_emac_post_load,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_STRUCT(mii, AwEmacState, 1, vmstate_mii, RTL8201CPState),
|
|
|
|
VMSTATE_UINT32(ctl, AwEmacState),
|
|
|
|
VMSTATE_UINT32(tx_mode, AwEmacState),
|
|
|
|
VMSTATE_UINT32(rx_ctl, AwEmacState),
|
|
|
|
VMSTATE_UINT32(int_ctl, AwEmacState),
|
|
|
|
VMSTATE_UINT32(int_sta, AwEmacState),
|
|
|
|
VMSTATE_UINT32(phy_target, AwEmacState),
|
|
|
|
VMSTATE_FIFO8(rx_fifo, AwEmacState),
|
|
|
|
VMSTATE_UINT32(rx_num_packets, AwEmacState),
|
|
|
|
VMSTATE_UINT32(rx_packet_size, AwEmacState),
|
|
|
|
VMSTATE_UINT32(rx_packet_pos, AwEmacState),
|
|
|
|
VMSTATE_STRUCT_ARRAY(tx_fifo, AwEmacState, NUM_TX_FIFOS, 1,
|
|
|
|
vmstate_fifo8, Fifo8),
|
|
|
|
VMSTATE_UINT32_ARRAY(tx_length, AwEmacState, NUM_TX_FIFOS),
|
|
|
|
VMSTATE_UINT32(tx_channel, AwEmacState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static void aw_emac_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
dc->realize = aw_emac_realize;
|
|
|
|
dc->props = aw_emac_properties;
|
|
|
|
dc->reset = aw_emac_reset;
|
|
|
|
dc->vmsd = &vmstate_aw_emac;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo aw_emac_info = {
|
|
|
|
.name = TYPE_AW_EMAC,
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(AwEmacState),
|
|
|
|
.instance_init = aw_emac_init,
|
|
|
|
.class_init = aw_emac_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void aw_emac_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&aw_emac_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(aw_emac_register_types)
|