2012-04-02 17:39:23 +08:00
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/*
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* QEMU S/390 CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#ifndef QEMU_S390_CPU_QOM_H
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#define QEMU_S390_CPU_QOM_H
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2012-12-18 01:19:50 +08:00
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#include "qom/cpu.h"
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2012-04-02 17:39:23 +08:00
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#include "cpu.h"
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#define TYPE_S390_CPU "s390-cpu"
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#define S390_CPU_CLASS(klass) \
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OBJECT_CLASS_CHECK(S390CPUClass, (klass), TYPE_S390_CPU)
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#define S390_CPU(obj) \
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OBJECT_CHECK(S390CPU, (obj), TYPE_S390_CPU)
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#define S390_CPU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(S390CPUClass, (obj), TYPE_S390_CPU)
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/**
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* S390CPUClass:
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2013-01-16 11:00:41 +08:00
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* @parent_realize: The parent class' realize handler.
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2012-04-02 17:39:23 +08:00
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* @parent_reset: The parent class' reset handler.
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2013-07-25 22:45:51 +08:00
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* @load_normal: Performs a load normal.
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s390/cpu: split CPU reset into architectured functions
s390 provides several CPU resets:
- CPU reset, clears interrupts, stop processing, clears TLB, but does
not touch registers
- initial CPU reset, like CPU reset, but also clears PSW, prefix, FPC,
timer and control registers. It does not touch gprs, fprs and acrs (!)
- Power on reset: the full monty
wire up CPUClass reset to the full monty, but provide the lesser resets
as part of S390CPUClass.
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2013-06-28 16:51:09 +08:00
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* @cpu_reset: Performs a CPU reset.
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* @initial_cpu_reset: Performs an initial CPU reset.
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2012-04-02 17:39:23 +08:00
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*
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* An S/390 CPU model.
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*/
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typedef struct S390CPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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2013-01-16 11:00:41 +08:00
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DeviceRealize parent_realize;
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2012-04-02 17:39:23 +08:00
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void (*parent_reset)(CPUState *cpu);
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2013-07-25 22:45:51 +08:00
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void (*load_normal)(CPUState *cpu);
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s390/cpu: split CPU reset into architectured functions
s390 provides several CPU resets:
- CPU reset, clears interrupts, stop processing, clears TLB, but does
not touch registers
- initial CPU reset, like CPU reset, but also clears PSW, prefix, FPC,
timer and control registers. It does not touch gprs, fprs and acrs (!)
- Power on reset: the full monty
wire up CPUClass reset to the full monty, but provide the lesser resets
as part of S390CPUClass.
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2013-06-28 16:51:09 +08:00
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void (*cpu_reset)(CPUState *cpu);
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void (*initial_cpu_reset)(CPUState *cpu);
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2012-04-02 17:39:23 +08:00
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} S390CPUClass;
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/**
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* S390CPU:
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* @env: #CPUS390XState.
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*
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* An S/390 CPU.
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*/
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typedef struct S390CPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUS390XState env;
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} S390CPU;
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static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
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{
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2013-05-10 22:34:06 +08:00
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return container_of(env, S390CPU, env);
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2012-04-02 17:39:23 +08:00
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}
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#define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
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2013-02-23 02:10:01 +08:00
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#define ENV_OFFSET offsetof(S390CPU, env)
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2012-04-02 17:39:23 +08:00
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2014-09-30 16:58:42 +08:00
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#ifndef CONFIG_USER_ONLY
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extern const struct VMStateDescription vmstate_s390_cpu;
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#endif
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2013-02-02 17:57:51 +08:00
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void s390_cpu_do_interrupt(CPUState *cpu);
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2014-09-14 00:45:19 +08:00
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bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req);
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2013-05-27 07:33:50 +08:00
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void s390_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
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int flags);
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2013-07-10 21:26:46 +08:00
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int s390_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
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int cpuid, void *opaque);
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int s390_cpu_write_elf64_qemunote(WriteCoreDumpFunction f,
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CPUState *cpu, void *opaque);
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2013-06-30 00:55:54 +08:00
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hwaddr s390_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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2012-09-03 19:09:10 +08:00
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hwaddr s390_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
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2013-06-29 10:18:45 +08:00
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int s390_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int s390_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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2014-08-29 21:52:16 +08:00
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void s390_cpu_gdb_init(CPUState *cs);
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2013-02-02 17:57:51 +08:00
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2012-04-02 17:39:23 +08:00
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#endif
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